Integrated circuit inductors

• US 7,135,951 B1
• Filed: 07/15/2003
• Issued: 11/14/2006
• Est. Priority Date: 07/15/2003
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Rahim, Irfan, Sidhu, Lakhbeer S.
• Primary Examiner(s): MAI, ANH T
• Application Number:
  US10/620,859
• Time in Patent Office: 1,218 Days
• Field of Search: 336/223, 336/200, 336/232, 257/E21.001, 257/E21.022, 257/E27.046, 257/E21.016, 296/021, 296/05, 296/06
• US Class Current: 336/200
• CPC Class Codes: H01F 17/0013 with stacked layers
• CPC Class Codes: H01F 2017/002 Details of via holes for interconnecting the layers
• CPC Class Codes: H01F 2017/0053 with means to reduce eddy currents
• CPC Class Codes: H01F 27/34 Special means for preventing or reducing unwanted electric or magnetic effects, e.g. no-load losses, reactive currents, harmonics, oscillations, leakage fields
• CPC Class Codes: H01F 27/36 Electric or magnetic shields or screens movable for varying inductance H01F21/10
• CPC Class Codes: H01F 27/363 made of electrically conductive material
• CPC Class Codes: H01F 27/40 Structural association with built-in electric component, e.g. fuse
• CPC Class Codes: H01F 41/041 Printed circuit coils apparatus or processes for manufacturing printed circuits in general H05K3/00
• CPC Class Codes: H01L 21/761 PN junctions
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10T 29/4902 Electromagnet, transformer or inductor
• CPC Class Codes: Y10T 29/49071 by winding or coiling

Abstract

Integrated circuit inductors may be formed using a spiral layout on the surface of an interconnect dielectric stack. Conductive lines from two or more metal layers in the interconnect stack may be electrically connected using one or more via trenches. The via trench interconnection arrangement reduces the resistance of the inductor and increases the inductor'"'"'s Q-factor. The Q-factor of the inductor may also be increased by placing a region of n-type and p-type wells or a metal plate region beneath the inductor to reduce power losses during operation. Shallow trench isolation may be used to reduce eddy currents and increase Q. The effects of copper dishing and trench blow-out may be used during inductor fabrication. A dual damascene fabrication process may be used.

Claims

1. An integrated circuit inductor formed in an interconnect dielectric stack on an integrated circuit, comprising:

at least two metal-layer conductive lines that run parallel to each other in respective metal-layer dielectric layers in the interconnect dielectric stack; and

at least one via-trench conductive line in a via-trench dielectric layer in the interconnect stack, wherein the via-trench conductive line lies between the two metal-layer conductive lines, runs parallel to the two metal-layer conductive lines, and electrically connects the two metal-layer conductive lines.

2. The integrated circuit inductor defined in claim 1 wherein the metal-layer conductive lines and the via-trench conductive line comprise copper.

3. The integrated circuit inductor defined in claim 1 wherein the metal-layer conductive lines each form a spiral between first and second inductor terminals.

4. The integrated circuit inductor defined in claim 1 wherein there are at least three vertically-aligned metal-layer conductive lines that run parallel to each other, each in a different respective metal-layer dielectric layer in the interconnect dielectric stack, and wherein there are at least two sets of via-trench conductive lines, each set having at least one via-trench conductive line that electrically connects two of the three metal-layer conductive lines.

5. The integrated circuit inductor defined in claim 1 comprising at least two via-trench conductive lines between the two metal-layer conductive lines, wherein the two via-trench conductive lines electrically connect the two metal-layer conductive lines.

6. The integrated circuit inductor defined in claim 1 comprising at least two via-trench conductive lines between the two metal-layer conductive lines that electrically connect the two metal-layer conductive lines, wherein each via-trench conductive line has a bottom width and an upper width and wherein the bottom widths are less than the upper widths so that the via trenches merge at the top of the via-trench conductive lines.

7. The integrated circuit inductor defined in claim 1 wherein each of the metal-layer conductive lines has a length and the via-trench conductive line has a length, and wherein the length of the via-trench conductive line is equal to the length of the metal-layer conductive lines.

8. The integrated circuit inductor defined in claim 1 wherein the metal-layer conductive lines and the via-trench conductive line comprise copper and wherein the metal-layer conductive lines and via-trench conductive line are formed using a damascene semiconductor fabrication process.

9. The integrated circuit inductor defined in claim 1 wherein the metal-layer conductive lines and the via-trench conductive line comprise copper and wherein at least one of the metal-layer conductive lines and the via-trench conductive lines are formed using a dual-damascene semiconductor fabrication process.

10. The integrated circuit inductor defined in claim 1 wherein the interconnect dielectric stack has a top metal-layer dielectric layer, and wherein one of the metal-layer conductive lines is formed in the top metal-layer dielectric layer.

11. The integrated circuit inductor defined in claim 1 wherein the metal-layer conductive lines comprise upper and lower parallel metal-layer conductive lines in the interconnect dielectric stack and wherein the lower parallel metal-layer conductive line has a concave upper surface due to dishing and the upper parallel metal-layer conductive line has a convex lower surface from being formed on top of the concave upper surface of the lower metal-layer conductive line.

12. The integrated circuit inductor defined in claim 1 wherein the interconnect dielectric stack lies on the surface of a semiconductor substrate, the integrated circuit inductor further comprising a metal plate between the two metal layer conductive lines and the surface of the semiconductor substrate to reduce electromagnetic field interactions between the integrated circuit inductor and the semiconductor substrate.

13. The integrated circuit inductor defined in claim 1 wherein the interconnect dielectric stack lies on the surface of a semiconductor substrate, the integrated circuit inductor further comprising a plurality of n-type and p-type wells at the surface of the semiconductor substrate that form a plurality of reverse-biased diodes that block eddy currents from flowing in the semiconductor substrate when the integrated circuit inductor is operated.

14. The integrated circuit inductor defined in claim 13 wherein the n-type and p-type wells include at least some deep wells having depths greater than one micron.

15. The integrated circuit inductor defined in claim 13 further comprising a region of shallow trench isolation that is formed on the surface of the semiconductor substrate between the n-type and p-type wells and the interconnect dielectric stack.

16. The integrated circuit inductor defined in claim 13 wherein the two metal-layer conductive lines comprise at least two square metal-layer spirals interconnected by a square spiral via trench and wherein the square spirals have lateral dimensions of less than 200 microns.

17. An integrated circuit inductor formed in an interconnect dielectric stack on an integrated circuit, comprising:

at least three spiral metal-layer conductive lines that run parallel to each other in respective metal-layer dielectric layers in the interconnect dielectric stack; and

at least two via-trench conductive lines each of which lies in a via-trench dielectric layer in the interconnect stack, wherein each via-trench conductive line lies between a respective two of the metal-layer conductive lines, runs parallel to those two metal-layer conductive lines, and electrically connects those two metal-layer conductive lines.

18. The integrated circuit inductor defined in claim 17 wherein the metal-layer conductive lines and the via-trench conductive lines comprise copper and wherein the metal-layer conductive lines and the via-trench conductive lines are formed using a dual-damascene semiconductor fabrication process.

19. An integrated circuit inductor formed in an interconnect dielectric stack that lies on the surface of a semiconductor substrate in an integrated circuit, comprising:

at least two metal-layer conductive lines that run parallel to each other in respective metal-layer dielectric layers in the interconnect dielectric stack;

at least one conductor in a via-trench dielectric layer in the interconnect stack that electrically connects the two metal-layer conductive lines; and

a region of shallow trench isolation that is formed on the surface of the semiconductor substrate under the two metal-layer conductive lines, wherein the conductor comprises a via-trench conductive line that runs parallel to the metal-layer conductive lines.

20. The integrated circuit inductor defined in claim 19 further comprising a plurality of n-type and p-type wells in the semiconductor substrate under the two metal-layer conductive lines that form a plurality of reverse-biased diodes that block eddy currents from flowing in the semiconductor substrate when the integrated circuit inductor is operated.

21. The integrated circuit inductor defined in claim 19 wherein the two metal-layer conductive lines and the via-trench conductive line are spiral.

22. A method of forming an integrated circuit inductor for an integrated circuit with a dielectric interconnect stack on a semiconductor substrate, comprising:

forming at least two vertically-aligned metal-layer conductive lines in respective metal-layer dielectric layers in the dielectric interconnect stack using a damascene process; and

forming at least one via-trench conductive line in a via-layer dielectric layer in the dielectric interconnect stack using the damascene process, wherein the via-trench conductive line runs parallel to the two metal-layer conductive lines and electrically interconnects the two metal-layer conductive lines.

23. The method defined in claim 22 wherein the integrated circuit inductor has a Q-factor, the method further comprising:

forming the conductive inductor line in a spiral; and

forming a region of n-type and p-type wells beneath the spiral to prevent eddy currents from reducing the Q-factor during operation of the inductor.

24. The method defined in claim 22 further comprising forming a plurality of parallel via-trench conductive lines between the two metal-layer conductive lines.

25. The method defined in claim 24 further comprising forming a plurality of parallel via-trench grooves for the parallel via-trench conductive lines using etching, wherein forming the parallel via-trench grooves comprises allowing the parallel via-trench grooves to merge during etching.

26. The method defined in claim 22 further comprising using a copper dual-damascene fabrication process to form the metal-layer conductive lines and the via-trench conductive line.