Systems and methods for mismatch cancellation in switched capacitor circuits

• US 7,136,006 B2
• Filed: 06/23/2005
• Issued: 11/14/2006
• Est. Priority Date: 12/16/2004
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Reyes, Alexander H., Koh, Jinseok
• Primary Examiner(s): Mai, Lam T.
• Application Number:
  US11/165,771
• Publication Number:
  US 20060132341A1
• Time in Patent Office: 509 Days
• Field of Search: 341139-172
• US Class Current: 341/172
• CPC Class Codes: H03M 3/458 Analogue/digital converters using delta-sigma modulation as an intermediate step
• CPC Class Codes: H03M 3/47 using time-division multiplexing

Abstract

Various circuits, systems and methods are disclosed for providing double-sampling sigma-delta modulator circuits. For example, circuits are disclosed that include an amplifier with an integrating capacitor, a switched capacitor conversion element that includes a single capacitor bank, and a control element that provides phase signaling that identifies at least two phases. In operation, charge present on the single capacitor bank is transferred to the integrating capacitor and the single capacitor bank is charged during one phase. During the other phase, charge present on the single capacitor bank is transferred to the integrating capacitor, and the single capacitor bank is discharged.

Claims

1. A double-sampling sigma-delta modulator circuit, the circuit comprising:

an amplifier including an integrating capacitor;

a switched capacitor conversion element including a single capacitor bank, wherein the single capacitor bank includes a first capacitive element and a second capacitive element; and

a control element, wherein the control element provides phase signaling that identifies at least a first phase and a second phase;

wherein during the first phase charge present on the single capacitor bank is transferred to the integrating capacitor, and the single capacitor bank is charged; and

wherein during the second phase charge present on the single capacitor bank is transferred to the integrating capacitor, and the single capacitor bank is discharged by electrically coupling a first plate of the first capacitive element to a first plate of the second capacitive element and electrically coupling a second plate of the first capacitive element and a second plate of the second capacitive element to the integrating capacitor.

2. The circuit of claim 1, wherein the switched capacitor conversion element is a double-sampled digital to analog converter.

3. The circuit of claim 1, wherein the circuit further comprises a p-path delay, wherein the p-path delay provides feedback to the amplifier, and wherein the p-path delay is implemented using two switched capacitor structures.

4. The circuit of claim 3, wherein the two switched capacitor structures provide a rotating sampling with one of the switched capacitor structures sampling an output of the amplifier, and the other switched capacitor structure transferring the past sampled output of the amplifier to the integrating capacitor.

5. The circuit of claim 1, wherein the circuit further comprises a q-path delay, wherein the q-path delay provides feedback to the amplifier, and wherein the q-path delay is implemented using three switched capacitor structures.

6. The circuit of claim 5, wherein the three switched capacitor structures provide a rotating sampling with a first of the switched capacitor structures sampling an output of the amplifier, a second of the switched capacitor structures holding the previously sampled output, and a third of the switched capacitor structures transferring the previously held output of the amplifier to the integrating capacitor.

7. The circuit of claim 1, wherein the circuit provides a transfer function substantially identical to a corresponding circuit using a dual switched capacitor element with two capacitor banks.

8. The circuit of claim 1, wherein the circuit is implemented in a deep sub-micron process.

9. The circuit of claim 8, wherein the deep sub-micron process has a feature size of less than 100 nanometers.

10. The circuit of claim 8, wherein the deep sub-micron process is a ninety nanometer digital CMOS process using metal-to-metal capacitors.

11. The circuit of claim 1, wherein the circuit substantially eliminates alternating gain effect.

12. A scalable, double-sampling sigma-delta modulator circuit, the circuit comprising:

an amplifier, wherein the amplifier includes an integrating capacitor;

a double-sampled digital to analog converter operable in a first phase and a second phase, wherein the double sampled digital to analog converter includes a sampling capacitor bank with a first capacitor and a second capacitor, and wherein the double-sampled digital to analog converter is coupled to the amplifier;

wherein during the first phase charge present on the sampling capacitor bank is transferred to the integrating capacitor, and the sampling capacitor bank is charged; and

wherein during the second phase charge present on the sampling capacitor bank is transferred to the integrating capacitor, and the sampling capacitor bank is discharged by electrically coupling a first plate of the first capacitor to a first plate of the second capacitor and electrically coupling a second plate of the first capacitor and a second plate of the second capacitor to the amplifier.

13. The circuit of claim 12, wherein the amplifier includes an integrating capacitor, wherein the double-sampled digital to analog converter includes a single switched capacitor structure with a single capacitor bank, and wherein the circuit further comprises:

a control element, wherein the control element provides phase signaling that identifies at least a first phase and a second phase

wherein during the second phase charge present on the single capacitor bank is transferred to the integrating capacitor, and the single capacitor bank is discharged.

14. The circuit of claim 12, wherein the circuit further comprises a p-path delay, wherein the p-path delay provides feedback to the amplifier, wherein the p-path delay is implemented using two switched capacitor structures, and wherein the two switched capacitor structures provide a rotating sampling with one of the switched capacitor structures sampling an output of the amplifier, and the other switched capacitor structure transferring the past sampled output of the amplifier to the integrating capacitor.

15. The circuit of claim 12, wherein the circuit further comprises a q-path delay, wherein the q-path delay provides feedback to the amplifier, wherein the q-path delay is implemented using three switched capacitor structures, and wherein the three switched capacitor structures provide a rotating sampling with a first of the switched capacitor structures sampling an output of the amplifier, a second of the switched capacitor structures holding the previously sampled output, and a third of the switched capacitor structures transferring the previously held output of the amplifier to the integrating capacitor.

16. The circuit of claim 12, wherein the circuit is implemented in a deep sub-micron process.

17. The circuit of claim 16, wherein the deep sub-micron process is a ninety nanometer digital CMOS process using metal-to-metal capacitors.

18. A double-sampling sigma-delta modulator circuit, the circuit comprising:

an amplifier including an integrating capacitor circuit;

a switched capacitor conversion element operable in a first phase and a second phase and including a single capacitor bank, wherein the switched capacitor conversion element is coupled to the amplifier; and

at least one delay circuit selected from a group consisting of;

a q-path delay circuit, wherein the q-path delay circuit provides feedback to the amplifier, wherein the q-path delay circuit is implemented using three switched capacitor structures; and

a p-path delay circuit, wherein the p-path delay circuit provides feedback to the amplifier, and wherein the p-path delay circuit is implemented using two switched capacitor structures;

wherein during the first phase charge present on the single capacitor bank is transferred to the integrating capacitor circuit, and the single capacitor bank is charged; and

wherein during the second phase charge present on the single capacitor bank is transferred to the integrating capacitor circuit, and the single capacitor bank is discharged.

19. The circuit of claim 18, wherein the three switched capacitor structures of the q-path delay circuit provide a rotating sampling with a first of the switched capacitor structures sampling an output of the amplifier, a second of the switched capacitor structures holding the previously sampled output, and a third of the switched capacitor structures transferring the previously held output of the amplifier to the integrating capacitor.

20. The circuit of claim 18, wherein the two switched capacitor structures of the p-path delay circuit provide a rotating sampling with one of the switched capacitor structures sampling an output of the amplifier, and the other switched capacitor structure transferring the past sampled output of the amplifier to the integrating capacitor.