Camera system for high-speed image processing including selection of at least one frame based on processed results

• US 7,136,097 B1
• Filed: 10/04/2000
• Issued: 11/14/2006
• Est. Priority Date: 10/04/1999
• Status: Expired due to Fees

• Current Assignee: Hamamatsu Photonics KK
• Original Assignee: Hamamatsu Photonics KK
• Inventors: Nakamura, Kazuhiro, Mukohzaka, Naohisa, Yamakawa, Hiroo, Toyoda, Haruyoshi, Mizuno, Seiichiro
• Primary Examiner(s): Vu, Ngoc-Yen
• Assistant Examiner(s): LAM, HUNG H
• Application Number:
  US10/089,192
• Time in Patent Office: 2,232 Days
• Field of Search: None
• US Class Current: 348/222.1
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof
• CPC Class Codes: H04N 25/707 Pixels for event detection
• CPC Class Codes: H04N 25/78 Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Abstract

The analog-to-digital converter array 13 includes one analog-to-digital converter 210 for each row of photodetectors 120 in the photodetector array 11. The image-processing unit 14 includes the plurality of processing circuits 400 for performing high-speed image processing. The signal converter 17 combines the output signals from the analog-to-digital converter array 13 with output signals from the image-processing unit 14. Under control of the control circuit 15 and the signal conversion controller 19, the signal converter 17 downconverts the composite signal at an important timing to a frame rate suitable for display on the monitor 18 and subsequently displays the signal on the monitor 18.

Claims

1. A camera for high-speed image processing, comprising:

a photodetector array having a plurality of photodetectors, which are arranged two-dimensionally in a plurality of rows and in a plurality of columns and which are divided into a plurality of blocks, the photodetector array repeatedly receiving optical images and generating output signals for optical images in a plurality of consecutive frames at a predetermined frame rate;

an analog-to-digital converter array receiving, from the photodetector array, the output signals for the optical images in the plurality of consecutive frames and generating digital signals in the plurality of consecutive frames, the analog-to-digital converter array including a plurality of analog-to-digital converters in one-on-one correspondence with the plurality of blocks in the photodetector array, each analog-to-digital converter performing analog-to-digital conversion of the output signals which are read sequentially from the photodetectors in a corresponding block;

an image-processing unit performing predetermined processes on the plurality of consecutive frames of the digital signals, which are successively transferred from the analog-to-digital converter array and which correspond to the signals outputted from the photodetectors, thereby generating processed result signals, other than the output signals for the optical signals, indicating results of the processes on the plurality of consecutive frames;

a selector selecting, among the plurality of consecutive frames, at least one frame based on the processed result signals for the plurality of consecutive frames obtained by the image-processing unit;

a signal converter converting, into an image signal of a desired frame rate, at least one of the processed result signal and the digital signal from the analog-to-digital converter array, the signal converter outputting the image signal; and

a signal conversion controller controlling the signal converter to perform the converting for the at least one frame selected by the selector.

2. A camera for high-speed image processing as claimed in claim 1, wherein the desired frame rate is lower than the predetermined frame rate.

3. A camera for high-speed image processing as claimed in claim 1, wherein the signal converter converts either one of the digital signal from the analog-to-digital converter array and the processed result signal, into the image signal of the desired frame rate, and outputs the image signal.

4. A camera for high-speed image processing as claimed in claim 1, wherein the signal converter combines the digital signal from the analog-to-digital converter array and the processed result signal, converts the combined signal into the image signal of the desired frame rate, and outputs the image signal.

5. A camera for high-speed image processing as claimed in claim 1, wherein the signal converter has a buffer memory at a signal input side thereof, the buffer memory storing at least one of the digital signal from the analog-to-digital converter array for at least several frames and the processed result signal for the at least several frames.

6. A camera for high-speed image processing as claimed in claim 1, further comprising a data buffer storing predetermined process data, the image-processing unit performing a predetermined parallel process, using the predetermined process data, onto the digital signals that are transferred from the analog-to-digital converter array and that correspond to the signals outputted from the photodetectors.

7. A camera for high-speed image processing as claimed in claim 1, wherein the plurality of analog-to-digital converters in the analog-to-digital converter array are provided in one-on-one correspondence with the plurality of rows of photodetectors in the photodetector array.

8. A camera for high-speed image processing as claimed in claim 1, wherein the plurality of analog-to-digital converters in the analog-to-digital converter array are provided in one-on-one correspondence with the plurality of columns of photodetectors in the photodetector array.

9. A camera for high-speed image processing as claimed in claim 1, wherein the image-processing unit includes a plurality of processors in one-to-one correspondence with the plurality of photodetectors, the plurality of processors performing parallel processes on the digital signals that are transferred from the analog-to-digital converter array and that correspond to the signals outputted from the plurality of photodetectors.

10. A camera for high-speed image processing as claimed in claim 1, wherein the image-processing unit includes at least one parallel processing circuit, each of the at least one parallel processing circuit performing a corresponding parallel process on the digital signals that are transferred from the analog-to-digital converter array and that correspond to the signals outputted from the photodetectors, thereby outputting a processed result signal indicative of the processed result, the selector selecting at least one frame based on at least one process result from the at least one parallel processing circuit, the signal converter converting at least one of the digital signal from the analog-to-digital converter array and the processed result signal obtained by the at least one parallel processing circuit, into the image signal of the desired frame rate, and outputting the image signal.

11. A camera for high-speed image processing as claimed in claim 10, wherein each of the at least one parallel processing circuit is provided with several processing elements in one-to-one correspondence with several blocks that make up at least a portion of all the plurality of blocks in the photodetector array, each of the several processing elements performing a predetermined parallel process on the digital signals that are transferred from the corresponding analog-to-digital converter and that are equivalent to the signals outputted from the photodetectors existing in the corresponding block.

12. A camera for high-speed image processing as claimed in claim 10, wherein the plurality of analog-to-digital converters in the analog-to-digital converter array are provided in one-to-one correspondence with the plurality of rows of photodetectors in the photodetector array, each of the at least one parallel processing circuits including several processing elements which are provided in one-to-one correspondence with several rows that make up at least a portion of all the plurality of rows in the photodetector array, each of the several processing elements performing a predetermined parallel process on digital signals that are transferred from the analog-to-digital converter array and that are equivalent to the signals outputted from the photodetectors in the corresponding row.

13. A camera for high-speed image processing as claimed in claim 1, wherein the selector selects at least one frame that includes one frame, processed results thereof obtained by the image-processing unit satisfying a predetermined condition.

14. A camera for high-speed image processing as claimed in claim 13, wherein the selector judges whether or not the processes results for the consecutive frames satisfy the predetermined condition, determines one frame, processed results thereof satisfying the predetermined condition, and selects at least one frame including the determined one frame.

15. A camera for high-speed image processing as claimed in claim 1, wherein the image processing unit performs a characteristic extracting process on the plurality of consecutive frames of the digital signals to determine characteristics of the consecutive frames, and

wherein the selector judges whether or not the extracted characteristics of the consecutive frames satisfy the predetermined condition, determines one frame, a characteristic thereof satisfying the predetermined condition, and selects at least one frame including the determined one frame.

16. A camera for high-speed image processing as claimed in claim 15, wherein the image processing unit performs a center of gravity calculation process on the plurality of consecutive frames of the digital signals to determine locations of the centers of gravity in the consecutive frames of the digital signals, and

wherein the selector judges whether or not the locations of centers of gravity in the consecutive frames satisfy the predetermined condition, determines one frame, the locations of the center of gravity thereof satisfying the predetermined condition, and selects at least one frame including the determined one frame.

17. A camera for high-speed image processing as claimed in claim 15, wherein the image processing unit performs a pattern matching process on the plurality of consecutive frames of the digital signals to generate the processed result signals indicating whether or not a predetermined pattern is detected in the consecutive frames, and

wherein the selector determines, based on the process result signals, one frame in which the predetermined pattern is detected, and selects at least one frame including the determined one frame.

18. A camera for high-speed image processing as claimed in claim 1, wherein the image-processing unit includes a parallel processing circuit that performs a parallel process on the plurality of consecutive frames of the digital signals to generate the processed result signals indicative of whether or not the consecutive frames of the digital signals satisfy a predetermined condition, and

wherein the selector selects at least one frame that includes one frame, a processed result signal thereof indicating that the one frame satisfies the predetermined condition.

19. A camera for high-speed image processing as claimed in claim 18, wherein the parallel processing circuit performs a center of gravity calculation process on the plurality of consecutive frames of the digital signals to generate the processed result signals indicative of the locations of the centers of gravity in the consecutive frames of the digital signals, and

wherein the selector judges, based on the processed result signals, whether or not locations of the centers of gravity of the consecutive frames satisfy the predetermined condition, determines one frame, the locations of the center of gravity thereof satisfying the predetermined condition, and selects at least one frame including the determined one frame.

20. A camera for high-speed image processing as claimed in claim 18, wherein the parallel processing circuit performs a pattern matching process on the plurality of consecutive frames of the digital signals to generate the processed result signals indicating whether or not a predetermined pattern is detected in the consecutive frames, and

wherein the selector determines, based on the processed result signals, one frame in which the predetermined pattern is detected, and selects at least one frame including the determined one frame.