Bank selectable parallel test circuit and parallel test method thereof

• US 7,136,315 B2
• Filed: 03/22/2005
• Issued: 11/14/2006
• Est. Priority Date: 03/22/2004
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Kang, Tae Jin
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): NGUYEN, DANG T
• Application Number:
  US11/085,173
• Publication Number:
  US 20050207245A1
• Time in Patent Office: 602 Days
• Field of Search: 365/201, 365/191, 365/230.03, 365/230.08, 365/230.01
• US Class Current: 365/201
• CPC Class Codes: G11C 2029/2602 Concurrent test
• CPC Class Codes: G11C 29/26 Accessing multiple arrays G11C29/24 takes precedence
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A parallel test circuit performs a selective test on a specific bank. The bank selectable parallel test circuit comprises a bank selecting control unit and a plurality of bank selecting units. The bank selecting control unit outputs a test mode control signal for selecting a test mode in response to a parallel test signal for controlling a parallel test and a compression test signal for controlling bank selection in the parallel test. Each of the plurality of bank selecting units, which correspond one by one to banks, selectively activates the corresponding banks in response to the test mode control signal and a bank selecting control signal.

Claims

1. A bank selectable parallel test circuit comprising:

a bank selecting control unit for outputting a test mode control signal for selecting a test mode in response to a parallel test signal for controlling a parallel test and a compression test signal for controlling bank selection in the parallel test; and

a plurality of bank selecting units, corresponding one by one to banks, for selectively activating the corresponding banks in response to the test mode control signal and a bank selecting control signal to selectively test a specific bank even in a parallel test mode.

2. The bank selectable parallel test circuit according to claim 1, wherein the bank selecting control unit outputs the test mode control signal when the parallel test signal is activated earlier than the compression test signal.

3. The bank selectable parallel test circuit according to claim 1, wherein each output signal from the plurality of bank selecting units is disabled by the parallel test signal at the parallel test mode.

4. The bank selectable parallel test circuit according to claim 1, wherein the plurality of bank selecting units simultaneously select all banks when the test mode control signal is activated, and select a specific bank in response to the bank selecting control signal when the test mode control signal is inactivated.

5. The bank selectable parallel test circuit according to claim 4, wherein each of the plurality of bank selecting units comprises:

first through fourth switching devices which are serially connected between a power voltage terminal and a ground voltage terminal and controlled by the test mode signal and the bank selecting control signal;

a fifth switching device which is connected in parallel to the second switching device and controlled by the bank selecting control signal; and

a sixth switching device whose one terminal is connected to an output terminal of the fifth switching device and whose other terminal receives a ground voltage and which is controlled by the test mode signal.

6. The bank selectable parallel test circuit according to claim 5, wherein the first switching device, the second switching device and the fifth switching device are individually PMOS transistors.

7. The bank selectable parallel test circuit according to claim 5, wherein the third switching device, the fourth switching device and the sixth switching device are individually NMOS transistors.

8. The bank selectable parallel test circuit according to claim 1, wherein the bank selecting control unit comprises a logic operation unit for outputting the test mode control signal according to the parallel test signal and the compression test signal.

9. The bank selectable parallel test circuit according to claim 8, wherein the logic operation unit comprises:

a first inverting unit for inverting the compression test signal;

a NAND gate for performing a NAND operation on the parallel test signal and an output signal from the first inverter; and

a second inverting unit for inverting an output signal from the NAND gate.

10. The bank selectable parallel test circuit according to claim 8, wherein the logic operation unit comprises:

a first inverting unit for inverting the parallel test signal; and

a NOR gate for performing a NOR operation on the compression test signal and an output signal from the first inverting unit.

11. The bank selectable parallel test circuit according to claim 8, wherein the logic operation unit comprises:

a NAND gate for performing a NAND operation on the parallel test signal and the compression test signal; and

an inverting unit for inverting an output signal from the NAND gate.

12. The bank selectable parallel test circuit according to claim 8, wherein the logic operation unit comprises:

a first inverting unit for inverting the parallel test signal;

a second inverting unit for inverting the compression test signal; and

a NOR gate for performing a NOR operation on output signal from the first inverting unit and the second inverting unit.

13. The bank selectable parallel test circuit according to claim 8, wherein the logic operation unit comprises a NOR gate for performing a NOR operation on the parallel test signal and the compression test signal.

14. The bank selectable parallel test circuit according to claim 8, wherein the logic operation unit comprises:

a first inverting unit for inverting the parallel test signal;

a NAND gate for performing a NAND operation on the compression test signal and an output signal from the first inverting unit; and

a second inverting unit for inverting an output signal from the NAND gate.

15. The bank selectable parallel test circuit according to claim 8, wherein the logic operation unit comprises:

an inverting unit for inverting the compression test signal; and

a NOR gate for performing a NOR operation on the parallel test signal and an output signal from the inverting unit.

16. A parallel test method comprising the steps of:

performing a logic operation on a parallel test signal for controlling a parallel test and a compression test signal for controlling bank selection to output a test mode control signal;

activating all bank selecting signals when the test mode control signal is activated to simultaneously select all banks, and activating a bank selecting signal corresponding to a specific bank in response to a bank selecting control signal when the test mode control signal is inactivated to select a corresponding bank; and

writing/reading data in the selected bank to test the selected bank.

17. The parallel test method according to claim 16, wherein a specific bank is selectively tested in response to the compression test signal even when the parallel test signal is applied.

18. The parallel test method according to claim 16, wherein the parallel test signal is activated earlier than the compression test signal.

19. The parallel test method according to claim 16, wherein each output signal from the plurality of bank selecting units is disabled by the parallel test signal at the parallel test mode.