Memory management unit architecture for switch fabric

• US 7,136,381 B2
• Filed: 06/19/2001
• Issued: 11/14/2006
• Est. Priority Date: 06/19/2000
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Tai, Daniel, Battle, James
• Primary Examiner(s): Pham, Chi
• Assistant Examiner(s): LY, ANH VU H
• Application Number:
  US09/883,213
• Publication Number:
  US 20020012341A1
• Time in Patent Office: 1,974 Days
• Field of Search: 370/391, 370/392, 370/395.41, 370/399.51, 370/352, 370/401, 370/412, 370/413, 370/402, 370/428, 370/429, 707/213, 707/250
• US Class Current: 370/389
• CPC Class Codes: H04L 12/18 for broadcast or conference , e.g. multicast
• CPC Class Codes: H04L 12/1881 with schedule organisation, e.g. priority, sequence management
• CPC Class Codes: H04L 12/5601 Transfer mode dependent, e.g. ATM
• CPC Class Codes: H04L 2012/5651 Priority, marking, classes
• CPC Class Codes: H04L 2012/5665 Interaction of ATM with other protocols
• CPC Class Codes: H04L 2012/5679 Arbitration or scheduling
• CPC Class Codes: H04L 2012/5681 Buffer or queue management
• CPC Class Codes: H04L 2012/5683 for avoiding head of line blocking
• CPC Class Codes: H04L 45/00 Routing or path finding of packets in data switching networks routing or path finding in wireless networks H04W40/00
• CPC Class Codes: H04L 45/245 Link aggregation, e.g. trunking
• CPC Class Codes: H04L 45/54 Organization of routing tables
• CPC Class Codes: H04L 45/745 Address table lookup; Address filtering
• CPC Class Codes: H04L 47/10 Flow control; Congestion control
• CPC Class Codes: H04L 47/2408 for supporting different services, e.g. a differentiated services [DiffServ] type of service
• CPC Class Codes: H04L 47/2425 for supporting services specification, e.g. SLA
• CPC Class Codes: H04L 47/2441 relying on flow classification, e.g. using integrated services [IntServ]
• CPC Class Codes: H04L 47/245 using preemption
• CPC Class Codes: H04L 47/286 Time to live
• CPC Class Codes: H04L 47/30 in combination with information about buffer occupancy at either end or at transit nodes
• CPC Class Codes: H04L 47/32 by discarding or delaying data units, e.g. packets or frames
• CPC Class Codes: H04L 47/6205 : Arrangements for avoiding head of line blocking
• CPC Class Codes: H04L 47/6215 : Individual queue per QOS, rate or priority
• CPC Class Codes: H04L 47/6225 : Fixed service order, e.g. Round Robin
• CPC Class Codes: H04L 49/101 : using crossbar or matrix
• CPC Class Codes: H04L 49/201 : Multicast operation; Broadcast operation
• CPC Class Codes: H04L 49/203 : ATM switching fabrics with multicast or broadcast capabilities
• CPC Class Codes: H04L 49/205 : Quality of Service based
• CPC Class Codes: H04L 49/25 : Routing or path finding in a switch fabric
• CPC Class Codes: H04L 49/254 : Centralised controller, i.e. arbitration or scheduling
• CPC Class Codes: H04L 49/30 : Peripheral units, e.g. input or output ports
• CPC Class Codes: H04L 49/309 : Header conversion, routing tables or routing tags
• CPC Class Codes: H04L 49/352 : Gigabit ethernet switching [GBPS]
• CPC Class Codes: H04L 49/608 : ATM switches adapted to switch variable length packets, e.g. IP packets
• CPC Class Codes: H04L 49/90 : Buffering arrangements
• CPC Class Codes: H04L 49/901 : using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9094 : Arrangements for simultaneous transmit and receive, e.g. simultaneous reading/writing from/to the storage element
• CPC Class Codes: Y02D 30/50 : in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A memory management unit (MMU) for a network switch fabric for forwarding data is disclosed. The MMU has an ingress port interface receiving portions of a data packet and an egress port interface, connected to ingress ports of the fabric through an ingress bus ring. The MMU also includes a cell packer, that groups packet data into cells and a packet pool memory, that stores cells received from the cell packer. The MMU also includes a cell unpacker, where the cell unpacker separates stored cells before releasing the cells to an egress port. The MMU also includes an egress scheduler communicating with the cell unpacker, where the egress scheduler determines which packet data should be retrieved from the packet pool memory according to priority rules. The priority rules can be a deficit round robin scheduling algorithm or a weighted round robin scheduling algorithm.

Claims

1. A memory management unit for a network switch fabric for forwarding data comprising:

an ingress port interface receiving portions of a data packet;

an egress port interface, connected to ingress ports of the fabric through an ingress bus ring;

a cell packer, where the cell packer groups packet data into cells;

a packet pool memory, where the packet pool memory stores cells received from the cell packer;

a cell unpacker, where the cell unpacker separates stored cells before releasing the cells to an egress port; and

wherein each port of the switch fabric has a memory for storing packet data and each port memory is configured such that the port memory for non-active ports buffers packet data for active ports upon request of the active ports.

2. A memory management unit as recited in claim 1, further comprising a plurality of egress port interfaces and wherein said ingress bus ring is configured such that outputs of one of the plurality of ingress port interfaces are physically connected to inputs of an adjacent one of the plurality of egress port interfaces.

3. A memory management unit as recited in claim 2, wherein each of said plurality of egress port interfaces has a same physical layout to facilitate placement and testing of the egress port interfaces.

4. A memory management unit as recited in claim 1, further comprising an egress scheduler communicating with the cell unpacker, where the egress scheduler determines which packet data should be retrieved from the packet pool memory according to priority rules.

5. A memory management unit as recited in claim 4, further comprising a series of transaction queues that store entry points to beginnings of packets in the packet pool memory and a link list array that provides a mapping of the cells in the packet pool memory;

wherein the link list array communicates with the transaction queues and the packet pool memory and the transaction queues communicates with the egress scheduler.

6. A method as recited in claim 5, wherein transaction queues are configured to monitor an age of packet data in the transaction queues and purge the packet data when the age is greater than a predetermined value.

7. A method as recited in claim 5, transaction queues are configured to determine if a class of service in the transaction queues has reached a limit and purge the data packet when one of the series of transaction queues has reached the limit.

8. A memory management unit as recited in claim 4, wherein the determined priority rules comprise a deficit round robin scheduling algorithm.

9. A memory management unit as recited in claim 4, wherein the determined priority rules comprise a weighted round robin scheduling algorithm.

10. A memory management unit as recited in claim 1, wherein the packer is configured to wait until a cell is filled before sending the cell to the packet pool memory.

11. A memory management unit as recited in claim 10, wherein a cell length of the cell is 640 bits.

12. A memory management unit as recited in claim 1, further comprising a memory error detector and a means for recovering from a detected memory error.

13. A network switch fabric having a memory management unit as recited in claim 1.

14. A network switch fabric as recited in claim 13, wherein the ingress bus ring comprises a series of buses, where the number of said series of buses is equal to the number of ingress ports.

15. A network switch fabric as recited in claim 14, wherein the ingress bus ring is configured to optimize power usage by examining an egress map for a packet arriving at one of the ingress ports and only forwarding packet data on the ring when a subsequent ingress port on the ring is specified in the egress map.

16. A network switch fabric as recited in claim 13, further comprising a message ring connected to ingress and egress port stations of the network switch fabric, used to pass messages between stations.

17. A network switch fabric as recited in claim 16, further comprising a central processing unit connected to the fabric and communicating with the ingress and egress port stations through the message ring.