Clock synchronization system and method for use in a scalable access node

• US 7,136,388 B2
• Filed: 06/27/2002
• Issued: 11/14/2006
• Est. Priority Date: 06/27/2002
• Status: Expired due to Fees

• Current Assignee: WSOU Investments, LLC (WSOU Holdings, LLC)
• Original Assignee: Alcatel SA (Nokia Corporation)
• Inventors: Blackburn, Bracy James, Friedrichs, Eric
• Primary Examiner(s): Vu, Huy D.
• Assistant Examiner(s): Shand, Roberta A.
• Application Number:
  US10/185,561
• Publication Number:
  US 20040001516A1
• Time in Patent Office: 1,601 Days
• Field of Search: 370/508, 370/395.62, 370/395.51
• US Class Current: 370/395.62
• CPC Class Codes: H04J 3/0691 Synchronisation in a TDM node

Abstract

A clock synchronization scheme for use with an access network element having scalable architecture. A point-to-point, high-speed communication link provided between two adjacent banks of the access network element logically interconnects a plurality of banks in a linear stack, thereby creating a stackplane hierarchy for local traffic. A primary bank includes a central master timing and frame alignment control block operable based on a master reference clock. A secondary bank immediately coupled to the primary bank is operable to synchronize its local clock based on a delay preset signal provided by the primary bank. Each remaining secondary bank is operable to synchronize its local clock based on the delay preset signal provided by a local master timing control block disposed in the secondary bank immediately above it.

Claims

1. A clock synchronization system for use in an access network element having a primary bank and a plurality of secondary banks interlinked via an interbank communication link, comprising:

a central master timing and frame alignment control block disposed in said primary bank, said central master timing and frame alignment control block operating based on a master reference clock to determine a delay preset with respect to a slave timing and frame alignment control block disposed in a first level secondary bank coupled to said primary bank;

a local counter coupled to said slave timing and frame alignment control block disposed in said first level secondary bank, wherein said local counter is operable to generate an adjusted local clock based on said delay preset received from said central master timing and frame alignment control block; and

a local master timing and frame alignment control block disposed in said first level secondary bank, said local master timing and frame alignment control block operating responsive to said adjusted local clock to determine a delay preset with respect to a slave timing and frame alignment control block disposed in an adjacent secondary bank immediately below said first level secondary bank, wherein a local counter coupled to said slave timing and frame alignment control block disposed in said adjacent secondary bank is operable to generate an adjusted local clock based on said delay preset received from said first level secondary bank.

2. The clock synchronization system as set forth in claim 1, wherein said master reference clock is generated based on a free-running counter disposed in said primary bank.

3. The clock synchronization system as set forth in claim 1, wherein said master reference clock is provided by a node timing reference associated with said access network element.

4. The clock synchronization system as set forth in claim 3, wherein said node timing reference is derived from a transport network coupled to said primary bank.

5. The clock synchronization system as set forth in claim 3, wherein said node timing reference is derived from a building integrated timing supply (BITS) input.

6. The clock synchronization system as set forth in claim 1, wherein said delay preset provided by said central master timing and frame alignment control block is embedded in a Synchronous Optical Network (SONET)-compatible carrier associated with said interbank communication link disposed between said primary bank and said first level secondary bank.

7. The clock synchronization system as set forth in claim 6, wherein said central master timing and frame alignment control block includes:

means to generate a reference SYNC signal directed to said slave timing and frame alignment control block disposed in said first level secondary bank; and

means to compare said reference SYNC signal with a received SYNC signal generated by said slave timing and frame alignment control block towards said primary slave timing and frame alignment control block.

8. The clock synchronization system as set forth in claim 7, wherein said SONET-compatible carrier is operable at around 2.5 Gigabit/second.

9. The clock synchronization system as set forth in claim 7, wherein said SONET-compatible carrier includes a Time-Division Multiplex (TDM) data channel.

10. The clock synchronization system as set forth in claim 7, wherein said SONET-compatible carrier includes an Asynchronous Transfer Mode (ATM) data channel.

11. A clock synchronization method for use in an access network element having a primary bank and a plurality of secondary banks interlinked via an interbank communication link, comprising the steps:

providing a delay preset by a central master timing and frame alignment control block disposed in said primary bank to a slave timing and frame alignment control block disposed in a first level secondary bank coupled to said primary bank;

adjusting a local clock generated by a local counter that is coupled to said slave timing and frame alignment control block disposed in said first level secondary bank, wherein said local clock is operable to be adjusted based on said delay preset received from said central master timing and frame alignment control block;

synchronizing a local master timing and frame alignment control block disposed in said first level secondary bank based on said adjusted local clock; and

providing a delay preset by said local master timing and frame alignment control block operating responsive to said adjusted local clock to a slave timing and frame alignment control block disposed in an adjacent secondary bank immediately below said first level secondary bank, wherein a local counter coupled to said slave timing and frame alignment control block disposed in said adjacent secondary bank is operable to generate an adjusted local clock based on said delay preset received from said first level secondary bank, said adjusted local clock in said adjacent secondary bank operating to synchronize a local master timing and frame alignment control block disposed therein.

12. The clock synchronization method as set forth in claim 11, further comprising the step of continuing to synchronize each of remaining secondary banks with reference to a local master timing and frame alignment control block disposed in an adjacent secondary block immediately above it.

13. The clock synchronization method as set forth in claim 11, wherein said step of providing a delay preset by said central master timing and frame alignment control block further comprises the steps of:

generating, responsive to a master reference clock associated with said primary bank, a reference SYNC signal by said central master timing and frame alignment control block;

transmitting said reference SYNC signal to said slave timing and frame alignment control block disposed in said first level secondary bank;

generating, responsive to said reference SYNC signal, a response SYNC signal by said slave timing and frame alignment control block;

transmitting said response SYNC signal to said central master timing and frame alignment control block;

determining said delay preset based on comparing said reference and response SYNC signals by said central master timing and frame alignment control block; and

transmitting said delay preset to said slave timing and frame alignment control block disposed in said first level secondary bank in a Synchronous Optical Network (SONET)-compatible carrier associated with said interbank communication link disposed between said primary bank and said first level secondary bank.

14. The clock synchronization method as set forth in claim 13, wherein said step of providing a delay preset by said local master timing and frame alignment to a slave timing and frame alignment control block disposed in said adjacent secondary bank further comprises the steps of:

generating, responsive to said adjusted local clock of said first level secondary bank, a reference SYNC signal by said local master timing and frame alignment control block;

transmitting said reference SYNC signal to said slave timing and frame alignment control block disposed in said adjacent secondary bank;

generating, responsive to said reference SYNC signal transmitted by said local master timing and frame alignment control block, a response SYNC signal by said slave timing and frame alignment control block in said adjacent secondary bank;

transmitting said response SYNC signal to said local master timing and frame alignment control block in said first level secondary bank;

determining said delay preset based on comparing said reference and response SYNC signals by said local master timing and frame alignment control block; and

transmitting said delay preset to said slave timing and frame alignment control block disposed in said adjacent secondary bank in a SONET-compatible carrier associated with said interbank communication link disposed between said first level secondary bank and said adjacent secondary bank.

15. The clock synchronization method as set forth in claim 14, wherein said master reference clock is provided by a free-running counter.

16. The clock synchronization method as set forth in claim 14, wherein said master reference clock is provided by a node timing reference associated with said access network element.

17. The clock synchronization method as set forth in claim 16, wherein said node timing reference is derived from a transport network coupled to said primary bank.

18. The clock synchronization method as set forth in claim 16, wherein said node timing reference is derived from a building integrated timing supply (BITS) input.