DC offset correcting in a direct conversion or very low IF receiver

• US 7,136,431 B2
• Filed: 10/24/2002
• Issued: 11/14/2006
• Est. Priority Date: 10/24/2002
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Shi, Hong, Jensen, Henrik T.
• Primary Examiner(s): Bocure, Tesfaldet
• Application Number:
  US10/279,949
• Publication Number:
  US 20040081256A1
• Time in Patent Office: 1,482 Days
• Field of Search: 375/319, 375/316, 375/317, 455/325, 455/324.2, 398/203, 327/306, 327/307
• US Class Current: 375/319
• CPC Class Codes: H04L 25/062 Setting decision thresholds using feedforward techniques only

Abstract

A direct conversion or VLIF receiver corrects DC offset by, prior to receiving a burst of data, the receiver determines a coarse DC offset with the antenna of the receiver switched off. The receiver then adjusts an analog portion of the receiver (e.g., the output of the mixers) based on the coarse DC offset. The receiver then determines a gain setting of the receiver (e.g., for the low noise amplifier and/or programmable gain amplifiers) with the antenna on. The receiver then sets the gain of at least one gain stage of the receiver based on the gain setting. The receiver then determines a fine DC offset with the antenna off. The receiver then, while receiving a burst of data, subtracts the fine DC offset from the digital baseband or low IF signal prior to data recovery.

Claims

1. A method for DC offset correction in a direct conversion or very low intermediate frequency (VLIF) receiver, the method comprises:

prior to receiving a burst of data;

determining a coarse DC offset with an antenna of the receiver off;

adjusting an analog portion of the receiver based on the coarse DC offset;

determining gain setting of the receiver with the antenna on;

setting gain of at least one gain stage of the receiver based on the gain setting;

determining a fine DC offset with the antenna off; and

while receiving the burst of data, subtracting the fine DC offset from a digital baseband signal or digital low IF signal.

2. The method of claim 1, wherein the determining the coarse DC offset further comprises:

switching off the antenna;

sampling offsets of the analog portion of the receiver; and

holding the offsets of the analog portion of the receiver as the coarse DC offset.

3. The method of claim 2, wherein the sampling further comprises:

setting gain of a low noise amplifier of the analog portion and gain a programmable gain amplifier of the analog portion to a default gain setting.

4. The method of claim 1, wherein the determining the gain setting of the receiver further comprises:

measuring a received signal strength indication (RSSI) with the antenna on; and

establishing the gain setting based on the RSSI.

5. The method of claim 4, wherein the adjusting the gain of the at least one gain stage of the receiver further comprises:

adjusting gain of a low noise amplifier based on the RSSI; and

adjusting gain of a programmable gain amplifier based on the RSSI.

6. The method of claim 4, wherein the measuring the RSSI further comprises:

waiting a settling time after the antenna is enable before measuring the RSSI.

7. The method of claim 1, wherein the determining the fine DC offset further comprises:

measuring a residual DC offset via a low corner frequency digital low pass filter; and

holding the residual DC offset after expiration of a filter settling time as the fine DC offset.

8. The method of claim 7, wherein the measuring the residual DC offset further comprises:

waiting a predetermined period of time after the antenna has been turned off.

9. The method of claim 7 further comprises:

enabling the antenna after holding the residual DC offset.

10. A method for DC offset correction in a direct conversion or very low intermediate frequency (VLIF) receiver, the method comprises:

determining a coarse analog DC offset by;

disabling an antenna coupled to the receiver;

sampling an analog DC offset of an analog portion of the receiver; and

holding the analog DC offset as the coarse analog DC offset;

adjusting the analog portion of the receiver based on the coarse analog DC offset;

determining a gain setting for at least one gain stage of the receiver with the antenna enabled;

adjusting gain of the at least one gain stage based on the gain setting;

determining a fine digital DC offset; and

adjusting a digital portion of the receiver based on the fine digital DC offset.

11. The method of claim 10, wherein the determining a gain setting further comprises:

waiting an antenna enabling settling time;

after expiration of the antenna enabling settling time, measuring received signal strength indication (RSSI);

establishing the gain setting based on the RSSI; and

disabling the antenna.

12. The method of claim 11, wherein the adjusting gain of the at least one gain stage further comprises:

adjusting gain of a low noise amplifier of the at least one gain stage based on the RSSI; and

adjusting gain of a programmable gain amplifier of the at least one gain stage based on the RSSI.

13. The method of claim 11, wherein the determining a fine digital DC offset further comprises:

waiting the antenna enabling settling time;

after expiration of the antenna enabling settling time, sampling digital DC offset present in the digital portion of the receiver;

holding the sampled digital DC offset as the fine digital DC offset; and

enabling the antenna.

14. A receiver comprises:

processing module; and

memory operably coupled to the processing module, wherein the memory includes operational instructions that cause the processing module to;

prior to receiving a burst of data;

determine a coarse DC offset with an antenna of the receiver off;

adjust an analog portion of the receiver based on the coarse DC offset;

determine gain setting of the receiver with the antenna on;

set gain of at least one gain stage of the receiver based on the gain setting;

determine a fine DC offset with the antenna off; and

while receiving the burst of data, subtract the fine DC offset from a digital baseband signal or a digital low IF signal.

15. The receiver of claim 14, wherein the memory further comprises operational instructions that cause the processing module to determine the coarse DC offset by:

switching off the antenna;

sampling offsets of the analog portion of the receiver; and

holding the offsets of the analog portion of the receiver as the coarse DC offset.

16. The receiver of claim 15, wherein the memory further comprises operational instructions that cause the processing module to sample the offsets of the analog portion by:

setting gain of a low noise amplifier of the analog portion and gain a programmable gain amplifier of the analog portion to a default gain setting.

17. The receiver of claim 14, wherein the memory further comprises operational instructions that cause the processing module to determine the gain setting of the receiver by:

measuring a received signal strength indication (RSSI) with the antenna on; and

establishing the gain setting based on the RSSI.

18. The receiver of claim 17, wherein the memory further comprises operational instructions that cause the processing module to adjust the gain of the at least one gain stage of the receiver by:

adjusting gain of a low noise amplifier based on the RSSI; and

adjusting gain of a programmable gain amplifier based on the RSSI.

19. The receiver of claim 17, wherein the memory further comprises operational instructions that cause the processing module to measure the RSSI by:

waiting a settling time after the antenna is enable before measuring the RSSI.

20. The receiver of claim 14, wherein the memory further comprises operational instructions that cause the processing module to determine the fine DC offset by:

measuring a residual DC offset via a low corner frequency digital low pass filter; and

holding the residual DC offset after expiration of a filter settling time as the fine DC offset.

21. The receiver of claim 20, wherein the memory further comprises operational instructions that cause the processing module to measure the residual DC offset by:

waiting a predetermined period of time after the antenna has been turned off.

22. The receiver of claim 20, wherein the memory further comprises operational instructions that cause the processing module to:

enable the antenna after holding the residual DC offset.

23. A receiver comprises:

processing module; and

memory operably coupled to the processing module, wherein the memory includes operational instructions that cause the processing module to;

determine a coarse analog DC offset by;

disabling an antenna coupled to the receiver;

sampling analog DC offset of an analog portion of the receiver; and

holding the analog DC offset as the coarse analog DC offset;

adjust the analog portion of the receiver based on the coarse analog DC offset;

determine a gain setting for at least one gain stage of the receiver;

adjust gain of the at least one gain stage based on the gain setting;

determine a fine digital DC offset; and

adjust a digital portion of the receiver based on the fine digital DC offset.

24. The receiver of claim 23, wherein the memory further comprises operational instructions that cause the processing module to determine a gain setting by:

waiting an antenna enabling settling time;

after expiration of the antenna enabling settling time, measuring received signal strength indication (RSSI);

establishing the gain setting based on the RSSI; and

disabling the antenna.

25. The receiver of claim 24, wherein the memory further comprises operational instructions that cause the processing module to adjust gain of the at least one gain stage by:

adjusting gain of a low noise amplifier of the at least one gain stage based on the RSSI; and

adjusting gain of a programmable gain amplifier of the at least one gain stage based on the RSSI.

26. The receiver of claim 24, the memory further comprises operational instructions that cause the processing module to determine a fine digital DC offset by:

waiting the antenna enabling settling time;

after expiration of the antenna enabling settling time, sampling digital DC offset present in the digital portion of the receiver;

holding the sampled digital DC offset as the fine digital DC offset; and

enabling the antenna.