CMOS process polysilicon strip loaded waveguides with a two layer core

• US 7,136,563 B1
• Filed: 07/07/2005
• Issued: 11/14/2006
• Est. Priority Date: 06/24/2002
• Status: Expired due to Fees

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Luxtera Incorporated (Cisco Systems, Inc.)
• Inventors: Gunn, Lawrence C. III, Pinguet, Thierry J., Rattier, Maxime Jean
• Primary Examiner(s): Healy, Brian
• Assistant Examiner(s): EL SHAMMAA, MARY A
• Application Number:
  US11/177,169
• Time in Patent Office: 495 Days
• Field of Search: 385/129, 385/130, 385/131, 385/132
• US Class Current: 385/129
• CPC Class Codes: G02B 6/12004 Combinations of two or more optical elements
• CPC Class Codes: G02B 6/132 by deposition of thin films

Abstract

A standard CMOS process is used to fabricate optical, optoelectronic and electronic devices at the same time on a monolithic integrated circuit. A polysilicon strip loaded waveguide is used as an example to illustrate the invention. The waveguide has a two layer core made of a polysilicon strip on a silicon slab. In a standard CMOS process, a layer of metallic salicide is deposited for metallic contacts for electronic components, such as transistors. In the present invention, prior to the deposition of the salicide, a salicide blocking layer is selectively deposited for protecting silicon waveguide against damages. The salicide blocking layer is used as one layer of the cladding of a silicon waveguide.

Claims

1. An optical waveguide on a substrate, where the optical waveguide is comprised of:

a core comprised of;

a slab of monocrystalline silicon, where the slab and a silicon body of a transistor are formed from the same layer of monocrystalline silicon on the same substrate, and

a strip of polysilicon disposed on the slab of monocrystalline silicon, where the strip and a polysilicon gate for a transistor are formed at the same time from the same polysilicon, and

a cladding comprised of a plurality of dielectric materials,

where at least one of the plurality of dielectric materials is comprised of a salicide block layer used during the fabrication of a transistor.

2. The optical waveguide of claim 1, wherein the substrate is comprised of a layer of silicon dioxide disposed on a layer of monocrystalline silicon.

3. The optical waveguide of claim 2, wherein the substrate and the layer of monocrystalline silicon disposed on the substrate comprises a silicon on insulator (SOI) wafer.

4. The optical waveguide of claim 2, wherein the cladding includes a bottom layer comprised of the layer of silicon dioxide, where the silicon dioxide layer is used to electrically isolate the transistor formed on the substrate from the lower layer of monocrystalline silicon.

5. The optical waveguide of claim 1, wherein the substrate is comprised of:

a first layer comprised of monocrystalline silicon,

a second layer comprised of silicon dioxide disposed on the first layer,

a third layer comprised of monocrystalline silicon disposed on the second layer and

a fourth layer comprised of silicon dioxide disposed on the third layer.

6. The optical waveguide of claim 5, wherein the cladding includes a bottom layer comprised of the fourth layer of the substrate, where the fourth layer is used to electrically isolate the transistor formed on the substrate from the third layer.

7. The optical waveguide of claim 1, wherein the substrate is comprised of sapphire.

8. The optical waveguide of claim 1, wherein the substrate is comprised of silicon on nothing, and the waveguide core is formed from a top layer of silicon.

9. The optical waveguide of claim 1, wherein the cladding includes a bottom cladding comprised of a top layer of the substrate.

10. The optical waveguide of claim 1, wherein the cladding includes a layer of dielectric material formed at the same time as a sidewall passivation for the silicon body of a transistor.

11. The optical waveguide of claim 1, wherein the cladding includes a plurality of layers of dielectric material formed at the same time as a plurality of dielectric materials used as a gate spacer for a transistor.

12. The optical waveguide of claim 1, wherein the cladding includes a layer of dielectric material formed at the same time as a contact punch-through layer for a transistor.

13. The optical waveguide of claim 1, wherein the cladding includes a layer of dielectric material formed at the same time as an inter-level dielectric for a transistor.

14. The optical waveguide of claims 10, 11, 12 or 13, wherein the layer of dielectric material included in the cladding is selected from the group comprising:

silicon dioxide, silicon oxynitride or silicon nitride.

15. The optical waveguide of claim 1, wherein at least one of the plurality of dielectric materials is selected from a group of dielectrics used at the same time to form a dielectric element of a transistor, where the group of dielectrics comprises:

a contact punch-through layer, an inter-layer dielectric film, a gate spacer, a salicide block, a dielectric spacer, a sidewall passivation film, an isolation dielectric, an oxide spacer and a field oxide.

16. The optical waveguide of claim 15, wherein thermal oxidation is used to form a sidewall passivation film, where the sidewall passivation film is used as one of a plurality of dielectric materials for the optical waveguide and is formed at the same time as the sidewall passivation film for the body of a transistor.

17. The optical waveguide of claim 1, wherein at least one of the plurality of dielectric materials is selected from the group comprising:

SiO₂, SiCOH, SiCOF, Si₃N₄, SiON, BPSG and silicon-based materials including one or more of the following elements;

oxygen, carbon, nitrogen, hydrogen, boron, phosphorus, fluorine and arsenic.

18. The optical waveguide of claim 1, wherein the transistor is selected from the group comprising:

a CMOS transistor, a BiCMOS transistor, a bipolar junction transistor (BJT) and a junction FET (JFET) transistor.

19. The optical waveguide of claim 1, wherein the salicide block layer is used as a gate spacer during the fabrication of a transistor on the same substrate.