Method for non-invasive performance monitoring and tuning

• US 7,136,778 B2
• Filed: 09/02/2004
• Issued: 11/14/2006
• Est. Priority Date: 09/02/2004
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: McLaughlin, Mark David, Duron, Mike Conrad
• Primary Examiner(s): Assouad, Patrick J.
• Application Number:
  US10/932,700
• Publication Number:
  US 20060047475A1
• Time in Patent Office: 803 Days
• Field of Search: None
• US Class Current: 702/182
• CPC Class Codes: G06F 11/348 Circuit details, i.e. tracer hardware
• CPC Class Codes: G06F 11/3485 for I/O devices

Abstract

A non-invasive method, system, and computer product for monitoring I/O performance without using the RIO bus. When executing a performance benchmark run in a remote I/O drawer, the system logs into a bulk power controller, wherein the bulk power controller provides a communications path between the data processing system and the I/O drawer, and wherein the communications path allows the data processing system to access chip register information on the I/O drawer without using a RIO link. Using the communications path, the system may monitor I/O performance and obtain chip register information. The system may further increase performance by using software to detect a load imbalance. Through the communications path, the software is able to dynamically balance the load by changing the chip register settings to allow the initialization registers to handle the load more efficiently.

Claims

1. A method for monitoring input/output performance in a data processing system, comprising:

executing a performance benchmark run on the data processing system with a remote input/output drawer;

logging onto a bulk power controller in response to executing the performance benchmark run, wherein the bulk power controller provides a communications path between the data processing system and the remote input/output drawer, and wherein the communications path allows the data processing system to access chip register information on the remote input/output drawer without using a remote input/output link; and

obtaining the chip register information and monitoring input/output performance using the communications path.

2. The method of claim 1, further comprising:

detecting a load imbalance; and

dynamically balancing a load by changing settings within a chip register using the communications path.

3. The method of claim 2, wherein the chip register is an initialization register.

4. The method of claim 2, wherein changing the settings in the chip register allows chip logic to handle the load more efficiently.

5. The method of claim 1, wherein the chip registers include JTAG-accessible registers.

6. The method of claim 1, wherein the communications path allows the data processing system to monitor input/output performance when a remote input/output link is broken.

7. The method of claim 1, wherein the communications path includes an I²C link.

8. The method of claim 1, wherein one of an ethernet interface or System Power Control Network interface is used to connect the data processing system to the bulk power controller.

9. The method of claim 1, wherein the bulk power controller is connected to a distributed converter assembly within the remote input/output drawer using a RS422/UART link.

10. The method of claim 1, wherein the data processing system sends commands to the distributed converter assembly using the RS422/UART link.

11. A data processing system for monitoring input/output performance in a data processing system, comprising:

executing means for executing a performance benchmark run on the data processing system with a remote input/output drawer;

logging means for logging onto a bulk power controller in response to executing the performance benchmark run, wherein the bulk power controller provides a communications path between the data processing system and the remote input/output drawer, and wherein the communications path allows the data processing system to access chip register information on the remote input/output drawer without using a remote input/output link; and

obtaining means for obtaining the chip register information and monitoring input/output performance using the communications path.

12. The data processing system of claim 11, further comprising:

detecting means for detecting a load imbalance; and

balancing means for dynamically balancing a load by changing settings within a chip register using the communications path.

13. The data processing system of claim 12, wherein the chip register is an initialization register.

14. The data processing system of claim 12, wherein changing the settings in the chip register allows chip logic to handle the load more efficiently.

15. The data processing system of claim 11, wherein the chip registers include JTAG-accessible registers.

16. The data processing system of claim 11, wherein the communications path allows the data processing system to monitor input/output performance when a remote input/output link is broken.

17. The data processing system of claim 11, wherein the communications path includes an I²C link.

18. The data processing system of claim 11, wherein one of an ethernet interface or System Power Control Network interface is used to connect the data processing system to the bulk power controller.

19. The data processing system of claim 11, wherein the bulk power controller is connected to a distributed converter assembly within the remote input/output drawer using a RS422/UART link.

20. The data processing system of claim 11, wherein the data processing system sends commands to the distributed converter assembly using the RS422/UART link.

21. A computer program product in a computer readable medium for monitoring input/output performance in a data processing system, the computer program product comprising:

first instructions for executing a performance benchmark run on the data processing system with a remote input/output drawer;

second instructions for logging onto a bulk power controller in response to executing the performance benchmark run, wherein the bulk power controller provides a communications path between the data processing system and the remote input/output drawer, and wherein the communications path allows the data processing system to access chip register information on the remote input/output drawer without using a remote input/output link; and

third instructions for obtaining the chip register information and monitoring input/output performance using the communications path.

22. The computer program product of claim 21, further comprising:

fourth instructions for detecting a load imbalance; and

fifth instructions for dynamically balancing a load by changing settings within a chip register using the communications path.

23. The computer program product of claim 22, wherein the chip register is an initialization register.

24. The computer program product of claim 22, wherein changing the settings in the chip register allows the chip logic to handle the load more efficiently.

25. The computer program product of claim 21, wherein the chip registers include JTAG-accessible registers.

26. The computer program product of claim 21, wherein the communications path allows the data processing system to monitor input/output performance when a remote input/output link is broken.

27. The computer program product of claim 21, wherein the communications path includes an I²C link.

28. The computer program product of claim 21, wherein one of an ethernet interface or System Power Control Network interface is used to connect the data processing system to the bulk power controller.

29. The computer program product of claim 21, wherein the bulk power controller is connected to a distributed converter assembly within the remote input/output drawer using a RS422/UART link.

30. The computer program product of claim 21, wherein the data processing system sends commands to the distributed converter assembly using the RS422/UART link.

31. A data processing system for monitoring input/output performance in a data processing system, comprising:

a remote input/output drawer;

a bulk power controller, wherein the bulk power controller provides a communications path between the data processing system and the remote input/output drawer, and wherein the communications path allows the data processing system to access chip register information on the remote input/output drawer without using a remote input/output link; and

a service processor, wherein the service processor logs onto the bulk power controller in response to executing a performance benchmark run on the data processing system with the remote input/output drawer, and wherein the service processor obtains the chip register information and monitors input/output performance using the communications path.

32. The data processing system of claim 31, wherein the service processor, responsive to detecting a load imbalance, dynamically balances a load by changing settings within a chip register using the communications path.