Method and apparatus for evaluating and optimizing a signaling system

• US 7,137,048 B2
• Filed: 10/12/2001
• Issued: 11/14/2006
• Est. Priority Date: 02/02/2001
• Status: Expired due to Term

• Current Assignee: Rampart Asset Management LLC
• Original Assignee: Rambus Inc.
• Inventors: Zerbe, Jared, Chau, Pak Shing, Stonecypher, William Franklin
• Primary Examiner(s): Lamarre, Guy
• Assistant Examiner(s): Trimmings, John P.
• Application Number:
  US09/976,170
• Publication Number:
  US 20030084385A1
• Time in Patent Office: 1,859 Days
• Field of Search: 714/715
• US Class Current: 714/715
• CPC Class Codes: G01R 31/31703 Comparison aspects, e.g. signature analysis, comparators concerning scan tests G01R31/318566; concerning testers G01R31/3193
• CPC Class Codes: G01R 31/31717 Interconnect testing by scan techniques see G01R31/31855
• CPC Class Codes: G01R 31/3183 Generation of test inputs, e.g. test vectors, patterns or sequences
• CPC Class Codes: G06F 11/221 to test buses, lines or interfaces, e.g. stuck-at or open line faults
• CPC Class Codes: H04B 3/32 Reducing cross-talk, e.g. by compensating

Abstract

A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the invention may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the invention may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.

Claims

1. A transmit circuit comprising:

a transmit data storage element configured to receive data from a transmit data input and sequentially transmit a transmit data output signal when the transmit circuit is operating in a normal mode, the transmit data storage element further configured to provide a repeating pattern signal when the transmit circuit is operating in a test mode, the transmit circuit sequentially transmitting the transmit data output signal based on the repeating pattern signal when the transmit circuit is operating in the test mode, wherein the transmit data storage element is loaded from the transmit data input to initialize the test mode.

2. The transmit circuit of claim 1 wherein the transmit data storage element comprises a shift register.

3. The transmit circuit of claim 1 further comprising:

a test loop coupled to the transmit data storage element when the transmit circuit is operating in the test mode, the test loop providing feedback to allow the transmit data storage element to provide the repeating pattern signal.

4. The transmit circuit of claim 1 wherein the repeating pattern signal has a data length greater than a data capacity of the transmit data storage element.

5. The transmit circuit of claim 1 wherein the repeating pattern signal represents a sequence of data bits, the transmit data storage element storing each of the data bits.

6. The transmit circuit of claim 1 wherein, when the transmit data storage element is divided into transmit data storage sub-elements during operation in the normal mode, the transmit data storage sub-elements are combined as the transmit data storage element for providing the repeating pattern signal when the transmit circuit is operating in the test mode.

7. The transmit circuit of claim 1 wherein the transmit data storage element is loaded via a parallel transmit load input.

8. The transmit circuit of claim 1 wherein the transmit circuit receives an adjustment signal from a receive circuit, the receive circuit receiving the transmit data output signal, the transmit circuit adjusting a parameter of the transmit data output signal based on the adjustment signal.

9. The transmit circuit of claim 8 wherein the receive circuit is embodied in a first memory device and a second receive circuit is embodied in a second memory device.

10. The transmit circuit of claim 9 wherein the transmit circuit adjusts the parameter to a first value for communication with the first memory device and to a second value for communication with the second memory device.

11. A method for operating a transmit circuit to provide for evaluation of a digital signaling system comprising the steps of:

passing transmit data through the transmit circuit when the transmit circuit is operating in a normal mode; and

generating a transmit repeating pattern in the transmit circuit when the transmit circuit is operating in a test mode by uniting a plurality of pipeline structures within the transmit circuit into a transmit repeating pattern generator when the transmit circuit is operating in the test mode.

12. The method of claim 11 wherein the step of generating a transmit repeating pattern in the transmit circuit further comprises the step of:

preloading an initialization pattern into the transmit circuit.

13. The method of claim 11 wherein the step of passing transmit data through the transmit circuit further comprises the step of:

passing distinct data through each of the plurality of pipeline structures when the transmit circuit is operating in the normal mode.

14. The method of claim 11 further comprising the steps of:

receiving the transmit data in a receive circuit when the transmit circuit is operating in the normal mode; and

receiving the transmit repeating pattern in the receive circuit when the transmit circuit is operating in the test mode.

15. The method of claim 11 further comprising the steps of:

receiving the transmit data in a receive circuit when the transmit circuit is operating in the normal mode; and

receiving the transmit repeating pattern in a test receiver separate from the receive circuit when the transmit circuit is operating in the test mode.

16. A method for operating a receive circuit to provide for evaluation of a digital signaling system comprising the steps of:

passing receive data through the receive circuit when the receive circuit is operating in a normal mode; and

generating a receive repeating pattern in the receive circuit when the receive circuit is operating in a test mode by uniting a plurality of pipeline structures within the receive circuit into a receive repeating pattern generator when the receive circuit is operating in the test mode.

17. The method of claim 16 wherein the step of generating a receive repeating pattern in the receive circuit further comprises the step of:

preloading an initialization pattern into the receive circuit.

18. The method of claim 16 wherein the step of passing receive data through the receive circuit further comprises the step of:

passing distinct data through each of the plurality of pipeline structures when the receive circuit is operating in the normal mode.

19. The method of claim 16 further comprising the steps of:

transmitting the receive data to the receive circuit from a transmit circuit when the receive circuit is operating in the normal mode; and

transmitting a transmit repeating pattern to the receive circuit from the transmit circuit when the receive circuit is operating in the test mode.

20. The method of claim 16 further comprising the steps of:

transmitting the receive data to the receive circuit from a transmit circuit when the receive circuit is operating in the normal mode; and

transmitting a transmit repeating pattern to the receive circuit from a test transmitter separate from the transmit circuit when the receive circuit is operating in the test mode.

21. A transmit circuit comprising:

a transmit data storage element configured to receive parallel data from a transmit data input and sequentially transmit a serial transmit data output signal when the transmit circuit is operating in a normal mode, the transmit data storage element further configured to provide a repeating pattern signal when the transmit circuit is operating in a test mode, the transmit circuit sequentially transmitting the serial transmit data output signal based on the repeating pattern signal when the transmit circuit is operating in the test mode, wherein the transmit data storage element is loaded from the transmit data input to initialize the test mode.

22. A receive circuit comprising:

a receive data storage element configured to output a parallel receive data output signal based on a serial receive data input signal received at a receive data input when the receive circuit is operating in a normal mode, the receive data storage element further configured to provide a repeating pattern signal when the receive circuit is operating in a test mode; and

a comparison element configured to perform a comparison of a relationship between the repeating pattern signal and the serial receive data input signal received at the receive data input and to produce a comparison output signal based on the comparison when the receive circuit is operating in the test mode;

wherein the receive data storage element is loaded from the receive data input to initialize the test mode.