Methods and apparatus for minimizing current surges during integrated circuit testing
First Claim
Patent Images
1. An integrated circuit, comprising:
- a) a plurality of interconnected circuit elements;
b) a number of scan chains which are interconnected with the plurality of interconnected circuit elements, said number of scan chains providing paths through which test data is shifted into and/or out of the integrated circuit; and
c) current surge minimization circuitry which is interconnected with said plurality of interconnected circuit elements, whereby operation of said current surge minimization circuitry during operation of said number of scan chains minimizes current surges in said integrated circuit.
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Abstract
Structural testing can lead to high and abnormal current surges. Disclosed herein are methods for designing and testing an IC so that current surges therein may be minimized while the IC is being tested. One disclosed way to minimize current surges is by gating out shift induced node state transitions. Another disclosed way to minimize current surges is to operate two or more of an IC'"'"'s scan chains in parallel, but out-of-phase.
12 Citations
23 Claims
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1. An integrated circuit, comprising:
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a) a plurality of interconnected circuit elements; b) a number of scan chains which are interconnected with the plurality of interconnected circuit elements, said number of scan chains providing paths through which test data is shifted into and/or out of the integrated circuit; and c) current surge minimization circuitry which is interconnected with said plurality of interconnected circuit elements, whereby operation of said current surge minimization circuitry during operation of said number of scan chains minimizes current surges in said integrated circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An integrated circuit, comprising:
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a) a plurality of interconnected circuit elements; b) a number of scan chains which are interconnected with the plurality of interconnected circuit elements, said number of scan chains providing paths through which test data is shifted into and/or out of the integrated circuit; and c) means for minimizing current surges in said integrated circuit as said number of scan chains shift test data into and out of said plurality of interconnected circuit elements. - View Dependent Claims (10, 11)
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12. A computer program product, comprising:
a computer usable medium having computer readable program code means embodied therein for synthesizing current surge minimization circuitry, the computer readable program code comprising; i) program code for reading a circuit description file, the circuit description file comprising data which specifies current surge minimization constraints for a circuit which is described in the circuit description file, at least some of said current surge minimization constraints being defined for operation of the circuit during operation of at least one scan chain of the circuit; ii) rules and design elements for minimizing current surges in a circuit; and iii) program code for synthesizing current surge minimization circuitry using said design elements, in conformance with said current surge minimization constraints and said rules for minimizing current surges in a circuit. - View Dependent Claims (13)
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14. A method of designing an integrated circuit, comprising:
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a) providing the integrated circuit with a number of scan chains which provide paths through which test data is shifted into and/or out of the integrated circuit; and b) providing the integrated circuit with current surge minimization circuitry, and configuring said currant surge minimization circuitry to be operated during operation of said number of scan chains. - View Dependent Claims (15, 16, 17)
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18. A method of testing an integrated circuit, comprising:
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a) shifting test data through a number of scan chains of the integrated circuit; and b) during at least a portion of said shifting, applying current surge minimization signals to the integrated circuit. - View Dependent Claims (19, 20)
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21. A method of testing an integrated circuit, comprising:
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a) providing test data to at least two scan chains of the integrated circuit; and b) shifting test data through the at least two scan chains in parallel, but out-of-phase, while at least a portion of the test data is being provided to the at least two scan chains. - View Dependent Claims (22, 23)
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Specification