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Methods and apparatus for minimizing current surges during integrated circuit testing

  • US 7,137,052 B2
  • Filed: 07/19/2001
  • Issued: 11/14/2006
  • Est. Priority Date: 07/19/2001
  • Status: Active Grant
First Claim
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1. An integrated circuit, comprising:

  • a) a plurality of interconnected circuit elements;

    b) a number of scan chains which are interconnected with the plurality of interconnected circuit elements, said number of scan chains providing paths through which test data is shifted into and/or out of the integrated circuit; and

    c) current surge minimization circuitry which is interconnected with said plurality of interconnected circuit elements, whereby operation of said current surge minimization circuitry during operation of said number of scan chains minimizes current surges in said integrated circuit.

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