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Single stage implementation of min*, max*, min and /or max to perform state metric calculation in SISO decoder

  • US 7,137,059 B2
  • Filed: 01/02/2003
  • Issued: 11/14/2006
  • Est. Priority Date: 11/20/2002
  • Status: Expired due to Fees
First Claim
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1. An apparatus, comprising:

  • a preliminary calculation circuitry that is operable to;

    calculate a plurality of 2 element log correction values, each 2 element log correction value of the plurality of 2 element log correction values corresponds to 2 inputs of a plurality of inputs;

    add each 2 element log correction value of the plurality of 2 element log correction values to a first of its corresponding 2 inputs from among the plurality of inputs thereby generating at least a first value;

    add each 2 element log correction value of the plurality of 2 element log correction values to its a second of its corresponding 2 inputs from among the plurality of inputs thereby generating at least a second value; and

    determine a mm result or max result using the first value and the second value;

    a final log correction value calculation circuitry that is operable to calculate a final log correction value that corresponds to all inputs of the plurality of inputs; and

    an adder that is operable to sum the mm result or the max result and the final log correction value to calculate a min* result or a max* result that is employed when calculating a state metric for use in decoding a coded signal.

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