Method of information processing using three dimensional integrated circuits

• US 7,138,295 B2
• Filed: 12/18/2003
• Issued: 11/21/2006
• Est. Priority Date: 04/04/1997
• Status: Expired due to Fees

• Current Assignee: Elm 3DS Innovations LLC
• Original Assignee: ELM TECHNOLOGY CORPORATION
• Inventors: Leedy, Glenn J
• Primary Examiner(s): Picardat, Kevin M.
• Application Number:
  US10/742,387
• Publication Number:
  US 20040132231A1
• Time in Patent Office: 1,069 Days
• Field of Search: 438/109, 438/106, 438/107, 438/108, 438/618, 438/622, 438/637, 365/51, 365/63
• US Class Current: 438/109
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/8083 Solid-solid interdiffusion
• CPC Class Codes: H01L 2224/8384 Sintering
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/02 Semiconductor bodies ; Multistep manufacturing processes therefor
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

Claims

1. A method of information processing using a plurality of thinned substantially flexible integrated circuits held in a stacked relation to one another with a major portion of each of said plurality of thinned substantially flexible integrated circuits held in unmovable relation to one another, and interconnections electrically connecting at least two of the plurality of said thinned substantially flexible integrated circuits, the method comprising:

transferring a plurality of data bytes between the at least two of the plurality of said thinned substantially flexible integrated circuits.

2. The method of claim 1, wherein the interconnections electrically connecting the plurality of thinned substantially flexible integrated circuits are vertical interconnections internal to the stacked thinned substantially flexible integrated circuits.

3. The method of claim 1, wherein the plurality of thinned substantially flexible integrated circuits are made from one of a single crystal semiconductor material and polycrystalline semiconductor material.

4. The method of claim 1, wherein the plurality of thinned substantially flexible integrated circuits are made from at least one of active circuit devices and passive circuit devices.

5. The method of claim 1, wherein at least one of the plurality of thinned substantially flexible integrated circuits are made from a plurality of circuit layers with active devices.

6. The method of claim 1, wherein at least one of the plurality of thinned substantially flexible integrated circuits is caused to have a thickness of less than about 50 microns.

7. The method of claim 1, wherein at least one of the plurality of thinned substantially flexible integrated circuits is caused to have a thickness of less than about 10 microns.

8. The method of claim 1, wherein one of the plurality of thinned substantially flexible integrated circuits is made using a different process technology from one of the other thinned substantially flexible integrated circuits.

9. The method of claim 8, wherein the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EEPROM, EPROM, Ferroelectric and Giant Magneto Resistance.

10. The method of claim 1, further comprising performing two or more simultaneous and independent data transfers between any two of the plurality of thinned substantially flexible integrated circuits.

11. The method of claim 1, wherein at least two of the plurality of thinned substantially flexible integrated circuits are logic integrated circuits, further comprising performing the transfer of a plurality of data bytes between the logic integrated circuits.

12. The method of claim 1, wherein at least one of the plurality of thinned substantially flexible integrated circuits contains testing circuitry, further comprising using the testing circuitry for testing circuits on at least one other of the substantially flexible integrated circuits.

13. The method of claim 1, wherein at least one of the plurality of thinned substantially flexible integrated circuits contains at least one of a microprocessor, a graphics processor, a power management control circuitry and a content-addressable memory circuitry.

14. The method of claim 1, further comprising performing at least one of audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, ECC, logical to real address translation, graphical processing and database management processing.

15. The method of claim 1, wherein one of the plurality of thinned substantially flexible integrated circuits is a memory controller circuit and at least one of the thinned substantially flexible integrated circuits is an at least one memory circuit, further comprising the transfer of a plurality of data bytes between the memory controller circuit and the at least one memory circuit.

16. The method of claim 15, wherein the memory controller circuit performs programmable gate line address assignment of internal circuitry with respect to the at least one memory circuit.

17. The method of claim 15, further comprising:

the memory controller circuit testing the at least one memory circuit to identify faulty memory locations; and

configuring the memory controller circuit by changing an address mapping within the memory controller circuit to the at least one memory circuit such that at least one address previously mapped to a faulty memory location can be mapped away from the faulty memory location.

18. The method of claim 17, wherein at least one address previously mapped to a faulty memory location is mapped instead to an existing functional memory location.

19. The method of claim 17, wherein at least one address previously mapped to a faulty memory location is mapped instead to a null, non-existent memory location.

181. The method of claim 2, further comprising forming the vertical interconnections from at least one of the front surface and back surface of at least one of the plurality of the thinned substantially flexible integrated circuits.

182. The method of claim 2, further comprising forming the vertical interconnections from the front surface of at least one of the plurality of thinned substantially flexible integrated circuits.

183. The method of claim 182, further comprising thinning the at least one of the plurality of thinned substantially flexible integrated circuits until the vertical interconnections formed from the front surface are visible from the back surface.

184. The method of claim 182, further comprising thinning the at least one of the plurality of thinned substantially flexible integrated circuits, wherein the appearance on the back surface of the vertical interconnections formed from the front surface is used to control the thinning of the at least one of the plurality of thinned substantially flexible integrated circuits.

201. The method of claim 1, wherein at least one of the plurality of thinned substantially flexible integrated circuits is formed with a low stress dielectric, wherein the low stress dielectric is at least one of a silicon dioxide dielectric, an oxide of silicon dielectric and caused to have stress of about 5×

10⁸ dynes/cm² or less.

202. The method of claim 201, wherein the stress of the low stress dielectric is tensile.

20. A method of information processing using an integrated circuit and a plurality of thinned substantially flexible integrated circuits positioned in a stacked relation to one another with a major portion of each of said integrated circuit and said plurality of thinned substantially flexible integrated circuits held in unmovable relation to one another, and interconnections electrically connecting the integrated circuit and at least one of said plurality of thinned substantially flexible integrated circuits, the method comprising:

transferring a plurality of data bytes between the integrated circuit and at least one of said plurality of thinned substantially flexible integrated circuits.

21. The method of claim 20, wherein the interconnections electrically connecting the integrated circuit and the plurality of thinned substantially flexible integrated circuits are vertical interconnections internal to the stacked integrated circuit and thinned substantially flexible integrated circuits.

22. The method of claim 20, wherein the integrated circuit and the plurality of thinned substantially flexible integrated circuits are made from one of a single crystal semiconductor material and polycrystalline semiconductor material.

23. The method of claim 20, wherein the integrated circuit and the plurality of thinned substantially flexible integrated circuits are made from at least one of active circuit devices and passive circuit devices.

24. The method of claim 20, wherein at least one of the integrated circuit and the plurality of thinned substantially flexible integrated circuits are made from a plurality of circuit layers with active devices.

25. The method of claim 20, wherein at least one of the integrated circuit and the plurality of thinned substantially flexible integrated circuits is caused to have a thickness of less than about 50 microns.

26. The method of claim 20, wherein at least one of the integrated circuit and the plurality of thinned substantially flexible integrated circuits is caused to have a thickness of less than about 10 microns.

27. The method of claim 20, wherein one of the integrated circuit and the plurality of thinned substantially flexible integrated circuits is made using a different process technology from one of the other integrated circuit and the thinned substantially flexible integrated circuits.

28. The method of claim 27, wherein the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EEPROM, EPROM, Ferroelectric and Giant Magneto Resistance.

29. The method of claim 20, further comprising performing two or more simultaneous and independent data transfers between any two of the integrated circuit and the plurality of thinned substantially flexible integrated circuits.

30. The method of claim 20, wherein at least two of the integrated circuit and the plurality of thinned substantially flexible integrated circuits are logic integrated circuits, further comprising the transfer of a plurality of data bytes between the logic integrated circuits.

31. The method of claim 20, wherein at least one of the integrated circuit and the plurality of thinned substantially flexible integrated circuits contains testing circuitry, further comprising using the testing circuitry for testing circuits on at least one other of the integrated circuit and substantially flexible integrated circuits.

32. The method of claim 20, wherein at least one of the integrated circuit and the plurality of thinned substantially flexible integrated circuits contains at least one of a microprocessor, a graphics processor, a power management control circuitry and a content-addressable memory circuitry.

33. The method of claim 20, further comprising performing at least one of audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, ECC, logical to real address translation, graphical processing and database management processing.

34. The method of claim 20, wherein one of the integrated circuit and the plurality of thinned substantially flexible integrated circuits is a memory controller circuit and at least one of the integrated circuit and the plurality of thinned substantially flexible integrated circuits is an at least one memory circuit, further comprising the transfer of a plurality of data bytes between the memory controller circuit and the at least one memory circuit.

35. The method of claim 34, wherein the memory controller circuit performs programmable gate line address assignment of internal circuitry with respect to the at least one memory circuit.

36. The method of claim 34, further comprising:

the memory controller circuit testing the at least one memory circuit to identify faulty memory locations; and

configuring the memory controller circuit by changing an address mapping within the memory controller circuit to the at least one memory circuit such that at least one address previously mapped to a faulty memory location can be mapped away from the faulty memory location.

37. The method of claim 36, wherein at least one address previously mapped to a faulty memory location is mapped instead to an existing functional memory location.

38. The method of claim 36, wherein at least one address previously mapped to a faulty memory location is mapped instead to a null, non-existent memory location.

185. The method of claim 21, further comprising forming the vertical interconnections from at least one of the front surface and back surface of at least one of the plurality of thinned substantially flexible integrated circuits.

186. The method of claim 21, further comprising forming the vertical interconnections from the front surface of at least one of the plurality of thinned substantially flexible integrated circuits.

187. The method of claim 186, further comprising thinning the at least one of the plurality of thinned substantially flexible integrated circuits until the vertical interconnections formed from the front surface are visible from the back surface.

188. The method of claim 186, further comprising thinning the at least one of the plurality of thinned substantially flexible integrated circuits, wherein the physical appearance on the back surface of the vertical interconnections formed from the front surface is used to control the thinning of the at least one of plurality of thinned substantially flexible integrated circuits.

203. The method of claim 20, wherein at least one of the integrated circuit and the plurality of thinned substantially flexible integrated circuits is formed with a low stress dielectric, wherein the low stress dielectric is at least one of a silicon dioxide dielectric, an oxide of silicon dielectric and caused to have stress of about 5×

10⁸ dynes/cm² or less.

204. The method of claim 203, wherein the stress of the low stress dielectric is tensile.

39. A method of information processing using an integrated circuit and a plurality of circuit layers overlying the integrated circuit, and interconnections electrically connecting the integrated circuit and at least one of the plurality of said circuit layers, the method comprising:

transferring a plurality of data bytes between the integrated circuit and at least one of said plurality of circuit layers;

wherein the transfer of the plurality of data bytes occurs through vertical interconnections internal to the integrated circuit and the plurality of circuit layers.

40. The method of claim 39, wherein the integrated circuit and the plurality of circuit layers are made from one of a single crystal semiconductor material and polycrystalline semiconductor material.

41. The method of claim 39, wherein the integrated circuit and the plurality of circuit layers are made from at least one of active circuit devices and passive circuit devices.

42. The method of claim 39, wherein the integrated circuit is made from a plurality of circuit layers with active devices.

43. The method of claim 39, wherein at least one of the integrated circuit and the plurality of circuit layers is caused to have a thickness of less than about 50 microns.

44. The method of claim 39, wherein at least one of the integrated circuit and the plurality of circuit layers is caused to have a thickness of less than about 10 microns.

45. The method of claim 39, wherein one of the integrated circuit and the plurality of circuit layers is made using a different process technology from one of the other integrated circuit and circuit layers.

46. The method of claim 45, wherein the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EEPROM, EPROM, Ferroelectric and Giant Magneto Resistance.

47. The method of claim 39, further comprising performing two or more simultaneous and independent data transfers between any two of the integrated circuit and the plurality of circuit layers.

48. The method of claim 39, wherein at least two of the integrated circuit and the plurality of circuit layers are logic integrated circuits, further comprising the transfer of a plurality of data bytes between the logic integrated circuits.

49. The method of claim 39, wherein at least one of the integrated circuit and the plurality of circuit layers contains testing circuitry, further comprising using the testing circuitry for testing circuits on at least one other of the integrated circuit and circuit layers.

50. The method of claim 39, wherein at least one of the integrated circuit and the plurality of circuit layers contains at least one of a microprocessor, a graphics processor, a power management control circuitry and a content-addressable memory circuitry.

51. The method of claim 39, further comprising performing at least one of audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, ECC, logical to real address translation, graphical processing and database management processing.

52. The method of claim 39, wherein one of the integrated circuit and the plurality of circuit layers is a memory controller circuit and at least one of the integrated circuit and the circuit layers is an at least one memory circuit, further comprising the transfer of a plurality of data bytes between the memory controller circuit and the at least one memory circuit.

53. The method of claim 52, wherein the memory controller circuit performs programmable gate line address assignment of internal circuitry with respect to the at least one memory circuit.

54. The method of claim 52, further comprising:

the memory controller circuit testing the at least one memory circuit to identify faulty memory locations; and

configuring the memory controller circuit by changing an address mapping within the memory controller circuit to the at least one memory circuit such that at least one address previously mapped to a faulty memory location can be mapped away from the faulty memory location.

55. The method of claim 54, wherein at least one address previously mapped to a faulty memory location is mapped instead to an existing functional memory location.

56. The method of claim 54, wherein at least one address previously mapped to a faulty memory location is mapped instead to a null, non-existent memory location.

178. The method of claim 39, wherein the integrated circuit is a thinned substantially flexible integrated circuit.

205. The method of claim 39, wherein at least one of the integrated circuit and the plurality of circuit layers is formed with a low stress dielectric, wherein the low stress dielectric is at least one of a silicon dioxide dielectric, an oxide of silicon dielectric and caused to have stress of about 5×

10⁸ dynes/cm² or less.

206. The method of claim 205, wherein the stress of the low stress dielectric is tensile.

57. A method of information processing using a stacked integrated circuit having a plurality of thinned substantially flexible integrated circuit layers, the method comprising:

transferring information between any two of the plurality of integrated circuit layers;

wherein the transfer of information occurs through vertical interconnections internal to the stacked integrated circuit.

58. The method of claim 57, wherein the plurality of thinned substantially flexible integrated circuit layers are made from one of a single crystal semiconductor material and polycrystalline semiconductor material.

59. The method of claim 57, wherein the plurality of thinned substantially flexible integrated circuit layers are made from at least one of active circuit devices and passive circuit devices.

60. The method of claim 57, wherein at least one of the plurality of thinned substantially flexible integrated circuit layers are made from a plurality of circuit layers with active devices.

61. The method of claim 57, wherein at least one of the plurality of thinned substantially flexible integrated circuit layers is caused to have a thickness of less than about 50 microns.

62. The method of claim 57, wherein at least one of the plurality of thinned substantially flexible integrated circuit layers is caused to have a thickness of less than about 10 microns.

63. The method of claim 57, wherein one of the plurality of thinned substantially flexible integrated circuit layers is made using a different process technology from one of the other thinned substantially flexible integrated circuit layers.

64. The method of claim 63, wherein the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EEPROM, EPROM, Ferroelectric and Giant Magneto Resistance.

65. The method of claim 57, further comprising performing two or more simultaneous and independent data transfers between any two of the plurality of thinned substantially flexible integrated circuit layers.

66. The method of claim 57, wherein at least two of the plurality of thinned substantially flexible integrated circuit layers are logic integrated circuits, further comprising performing the transfer of a plurality of data bytes between the logic integrated circuits.

67. The method of claim 57, wherein at least one of the plurality of thinned substantially flexible integrated circuit layers contains testing circuitry, further comprising using the testing circuitry for testing circuits on at least one other of the substantially flexible integrated circuits.

68. The method of claim 57, wherein at least one of the plurality of thinned substantially flexible integrated circuit layers contains at least one of a microprocessor, a graphics processor, a power management control circuitry and a content-addressable memory circuitry.

69. The method of claim 57, further comprising performing at least one of audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, ECC, logical to real address translation, graphical processing and database management processing.

70. The method of claim 57, wherein one of the plurality of thinned substantially flexible integrated circuit layers is a memory controller circuit and at least one of the thinned substantially flexible integrated circuit layers is an at least one memory circuit, further comprising the transfer of a plurality of data bytes between the memory controller circuit and the at least one memory circuit.

71. The method of claim 70, wherein the memory controller circuit performs programmable gate line address assignment of internal circuitry with respect to the at least one memory circuit.

72. The method of claim 70, further comprising:

the memory controller circuit testing the at least one memory circuit to identify faulty memory locations; and

configuring the memory controller circuit by changing an address mapping within the memory controller circuit to the at least one memory circuit such that at least one address previously mapped to a faulty memory location can be mapped away from the faulty memory location.

73. The method of claim 72, wherein at least one address previously mapped to a faulty memory location is mapped instead to an existing functional memory location.

74. The method of claim 72, wherein at least one address previously mapped to a faulty memory location is mapped instead to a null, non-existent memory location.

189. The method of claim 57, further comprising forming the vertical interconnections from at least one of the front surface and back surface of at least one of the plurality of thinned substantially flexible integrated circuit layers.

190. The method of claim 57, further comprising forming the vertical interconnections from the front surface of at least one of the plurality of thinned substantially flexible integrated circuit layers.

191. The method of claim 190, further comprising thinning the at least one of the plurality of thinned substantially flexible integrated circuit layers until the vertical interconnections formed from the front surface are visible from the back surface.

192. The method of claim 190, further comprising thinning the at least one of the plurality of thinned substantially flexible integrated circuit layers, wherein the physical appearance on the back surface of the vertical interconnections formed from the front surface is used to control the thinning of the at least one of plurality of thinned substantially flexible integrated circuit layers.

207. The method of claim 57, wherein at least one of the plurality of thinned substantially flexible integrated circuit layers is formed with a low stress dielectric, wherein the low stress dielectric is at least one of a silicon dioxide dielectric, an oxide of silicon dielectric and caused to have stress of about 5×

10⁸ dynes/cm² or less.

208. The method of claim 207, wherein the stress of the low stress dielectric is tensile.

75. A method of information processing using a stacked integrated circuit having a first integrated circuit layer and a plurality of integrated circuit layers wherein the plurality of integrated circuit layers are formed overlying the first integrated circuit layer, the method comprising:

transferring information between any two of the first integrated circuit layer and the plurality of integrated circuit layers;

wherein the transfer of information occurs through vertical interconnections internal to the stacked integrated circuit.

76. The method of claim 75, wherein the first integrated circuit and the plurality of integrated circuit layers are made from one of a single crystal semiconductor material and polycrystalline semiconductor material.

77. The method of claim 75, wherein the first integrated circuit and the plurality of integrated circuit layers are made from at least one of active circuit devices and passive circuit devices.

78. The method of claim 75, wherein at least one of the first integrated circuit and the plurality of integrated circuit layers are made from a plurality of circuit layers with active devices.

79. The method of claim 75, wherein at least one of the first integrated circuit and the plurality of integrated circuit layers is caused to have a thickness of less than about 50 microns.

80. The method of claim 75, wherein at least one of the first integrated circuit and the plurality of integrated circuit layers is caused to have a thickness of less than about 10 microns.

81. The method of claim 75, wherein one of the first integrated circuit and the plurality of integrated circuit layers is made using a different process technology from one of the other first integrated circuit and the integrated circuit layers.

82. The method of claim 81, wherein the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EEPROM, EPROM, Ferroelectric and Giant Magneto Resistance.

83. The method of claim 75, further comprising performing two or more simultaneous and independent data transfers between any two of the first integrated circuit and the plurality of integrated circuit layers.

84. The method of claim 75, wherein at least two of the first integrated circuit and the plurality of integrated circuit layers are logic integrated circuits, further comprising the transfer of a plurality of data bytes between the logic integrated circuits.

85. The method of claim 75, wherein at least one of the first integrated circuit and the plurality of integrated circuit layers contains testing circuitry, further comprising using the testing circuitry for testing circuits on at least one other of the first integrated circuit and the integrated circuit layers.

86. The method of claim 75, wherein at least one of the first integrated circuit and the plurality of integrated circuit layers contains at least one of a microprocessor, a graphics processor, a power management control circuitry and a content-addressable memory circuitry.

87. The method of claim 75, further comprising performing at least one of audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, ECC, logical to real address translation, graphical processing and database management processing.

88. The method of claim 75, wherein one of the first integrated circuit and the plurality of integrated circuit layers is a memory controller circuit and at least one of the first integrated circuit and the integrated circuit layers is an at least one memory circuit, further comprising the transfer of a plurality of data bytes between the memory controller circuit and the at least one memory circuit.

89. The method of claim 88, wherein the memory controller circuit performs programmable gate line address assignment of internal circuitry with respect to the at least one memory circuit.

90. The method of claim 88, further comprising:

the memory controller circuit testing the at least one memory circuit to identify faulty memory locations; and

configuring the memory controller circuit by changing an address mapping within the memory controller circuit to the at least one memory circuit such that at least one address previously mapped to a faulty memory location can be mapped away from the faulty memory location.

91. The method of claim 90, wherein at least one address previously mapped to a faulty memory location is mapped instead to an existing functional memory location.

92. The method of claim 90, wherein at least one address previously mapped to a faulty memory location is mapped instead to a null, non-existent memory location.

179. The method of claim 75, wherein the first integrated circuit layer is a thinned substantially flexible integrated circuit layer.

209. The method of claim 75, wherein at least one of the first integrated circuit and the plurality of integrated circuit layers is formed with a low stress dielectric, wherein the low stress dielectric is at least one of a silicon dioxide dielectric, an oxide of silicon dielectric and caused to have stress of about 5×

10⁸ dynes/cm² or less.

210. The method of claim 209, wherein the stress of the low stress dielectric is tensile.

93. A method of information processing using a stacked integrated circuit memory having an at least one logic layer and an at least one thinned substantially flexible memory layer with a major portion of each of said at least one logic layer and said at least one thinned substantially flexible memory layer held in unmovable relation to one another, the method comprising:

initiating a memory access; and

during the memory access, transferring data through a plurality of vertical connections interconnecting the at least one logic layer and the at least one thinned substantially flexible memory layer.

94. The method of claim 93, wherein the vertical connections interconnecting the at least one logic layer and the at least one thinned substantially flexible memory layer are vertical interconnections internal to the stacked integrated circuit.

95. The method of claim 93, wherein the at least one logic layer and the at least one thinned substantially flexible memory layer are made from one of a single crystal semiconductor material and polycrystalline semiconductor material.

96. The method of claim 93, wherein the at least one logic layer and the at least one thinned substantially flexible memory layer are made from at least one of active circuit devices and passive circuit devices.

97. The method of claim 93, wherein at least one of the at least one logic layer and the at least one thinned substantially flexible memory layer are made from a plurality of circuit layers with active devices.

98. The method of claim 93, wherein at least one of the at least one logic layer and the at least one thinned substantially flexible memory layer is caused to have a thickness of less than about 50 microns.

99. The method of claim 93, wherein at least one of the at least one logic layer and the at least one thinned substantially flexible memory layer is caused to have a thickness of less than about 10 microns.

100. The method of claim 93, wherein the at least one thinned substantially flexible memory layer is made using a different process technology from the at least one logic layer.

101. The method of claim 100, wherein the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EEPROM, EPROM, Ferroelectric and Giant Magneto Resistance.

102. The method of claim 93, further comprising performing two or more simultaneous and independent data transfers between the at least one logic layer and the at least one thinned substantially flexible memory layer.

103. The method of claim 93, wherein the logic layer contains testing circuitry, further comprising using the testing circuitry for testing circuits on the at least one thinned substantially flexible memory layer.

104. The method of claim 93, wherein the at least one logic layer contains at least one of a microprocessor, a graphics processor, a power management control circuitry and a content-addressable memory circuitry.

105. The method of claim 93, further comprising performing at least one of audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, ECC, logical to real address translation, graphical processing and database management processing.

106. The method of claim 93, wherein the at least one logic layer is a memory controller circuit and the at least one thinned substantially flexible memory layer is an at least one memory circuit, further comprising the transfer of a plurality of data bytes between the memory controller circuit and the at least one memory circuit.

107. The method of claim 106, wherein the memory controller circuit performs programmable gate line address assignment of internal circuitry with respect to the at least one memory circuit.

108. The method of claim 106, further comprising:

the memory controller circuit testing the at least one memory circuit to identify faulty memory locations; and

configuring the memory controller circuit by changing an address mapping within the memory controller circuit to the at least one memory circuit such that at least one address previously mapped to a faulty memory location can be mapped away from the faulty memory location.

109. The method of claim 108, wherein at least one address previously mapped to a faulty memory location is mapped instead to an existing functional memory location.

110. The method of claim 108, wherein at least one address previously mapped to a faulty memory location is mapped instead to a null, non-existent memory location.

193. The method of claim 93, further comprising forming the vertical connections from at least one of the front surface and back surface of the at least one thinned substantially flexible memory layer.

194. The method of claim 93, further comprising forming the vertical connections from the front surface of the at least one thinned substantially flexible memory layer.

195. The method of claim 194, further comprising thinning the at least one thinned substantially flexible memory layer until the vertical connections formed from the front surface are visible from the back surface.

196. The method of claim 194, further comprising thinning the at least one thinned substantially flexible memory layer, wherein the physical appearance on the back surface of the vertical connections formed from the front surface is used to control the thinning of the at least one thinned substantially flexible memory layer.

211. The method of claim 93, wherein at least one of the at least one logic layer and the at least one thinned substantially flexible memory layer is formed with a low stress dielectric, wherein the low stress dielectric is at least one of a silicon dioxide dielectric, an oxide of silicon dielectric and caused to have stress of about 5×

10⁸ dynes/cm² or less.

212. The method of claim 211, wherein the stress of the low stress dielectric is tensile.

214. The method of claim 211, wherein the stress of the low stress dielectric is tensile.

111. A method of information processing using a stacked integrated circuit memory having an at least one logic layer and an at least one memory layer formed overlying the logic layer, the method comprising:

initiating a memory access; and

during the memory access, transferring data through a plurality of vertical connections internal to the stacked integrated circuit.

112. The method of claim 111, wherein the at least one logic layer and the at least one memory layer are made from one of a single crystal semiconductor material and polycrystalline semiconductor material.

113. The method of claim 111, wherein the at least one logic layer and the at least one memory layer are made from at least one of active circuit devices and passive circuit devices.

114. The method of claim 111, wherein at least one of the at least one logic layer and the at least one memory layer are made from a plurality of circuit layers with active devices.

115. The method of claim 111, wherein at least one of the at least one logic layer and the at least one memory layer is caused to have a thickness of less than about 50 microns.

116. The method of claim 111, wherein at least one of the at least one logic layer and the at least one memory layer is caused to have a thickness of less than about 10 microns.

117. The method of claim 111, wherein the at least one memory layer is made using a different process technology from the at least one logic layer.

118. The method of claim 117, wherein the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EEPROM, EPROM, Ferroelectric and Giant Magneto Resistance.

119. The method of claim 111, further comprising performing two or more simultaneous and independent data transfers between the at least one logic layer and the at least one memory layer.

120. The method of claim 111, wherein the logic layer contains testing circuitry, further comprising using the testing circuitry for testing circuits on the at least one memory layer.

121. The method of claim 111, wherein the at least one logic layer contains at least one of a microprocessor, a graphics processor, a power management control circuitry and a content-addressable memory circuitry.

122. The method of claim 111, further comprising performing at least one of audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, ECC, logical to real address translation, graphical processing and database management processing.

123. The method of claim 111, wherein the at least one logic layer is a memory controller circuit and the at least one memory layer is an at least one memory circuit, further comprising the transfer of a plurality of data bytes between the memory controller circuit and the at least one memory circuit.

124. The method of claim 123, wherein the memory controller circuit performs programmable gate line address assignment of internal circuitry with respect to the at least one memory circuit.

125. The method of claim 123, further comprising:

the memory controller circuit testing the at least one memory circuit to identify faulty memory locations; and

configuring the memory controller circuit by changing an address mapping within the memory controller circuit to the at least one memory circuit such that at least one address previously mapped to a faulty memory location can be mapped away from the faulty memory location.

126. The method of claim 125, wherein at least one address previously mapped to a faulty memory location is mapped instead to an existing functional memory location.

127. The method of claim 125, wherein at least one address previously mapped to a faulty memory location is mapped instead to a null, non-existent memory location.

213. The method of claim 111, wherein at least one of the at least one logic layer and the at least one memory layer is formed with a low stress dielectric, wherein the low stress dielectric is at least one of a silicon dioxide dielectric, an oxide of silicon dielectric and caused to have stress of about 5×

10⁸ dynes/cm² or less.

128. A method of information processing using a stacked integrated circuit having at least one logic integrated circuit and at least one thinned substantially flexible logic integrated circuit with a major portion of each of said at least one logic integrated circuit and said at least one thinned substantially flexible logic integrated circuit held in unmovable relation to one another, the method comprising:

initiating an information transfer; and

during the information transfer, simultaneously transferring a plurality of data bytes through a plurality of vertical connections interconnecting the at least one logic integrated circuit and the at least one thinned substantially flexible logic integrated circuit.

129. The method of claim 128, wherein the vertical connections interconnecting the at least one logic integrated circuit and the at least one thinned substantially flexible logic integrated circuit are vertical interconnections internal to the stacked integrated circuit.

130. The method of claim 128, wherein the at least one logic integrated circuit and the at least one thinned substantially flexible logic integrated circuit are made from one of a single crystal semiconductor material and polycrystalline semiconductor material.

131. The method of claim 128, wherein the at least one logic integrated circuit and the at least one thinned substantially flexible logic integrated circuit are made from at least one of active circuit devices and passive circuit devices.

132. The method of claim 128, wherein at least one of the at least one logic integrated circuit and the at least one thinned substantially flexible logic integrated circuit are made from a plurality of circuit layers with active devices.

133. The method of claim 128, wherein at least one of the at least one logic integrated circuit and the at least one thinned substantially flexible logic integrated circuit is caused to have a thickness of less than about 50 microns.

134. The method of claim 128, wherein at least one of the at least one logic integrated circuit and the at least one thinned substantially flexible logic integrated circuit is caused to have a thickness of less than about 10 microns.

135. The method of claim 128, further comprising performing two or more simultaneous and independent data transfers between the at least one logic integrated circuit and the at least one thinned substantially flexible logic integrated circuit.

136. The method of claim 128, wherein at least one of the at least one logic integrated circuit and the at least one thinned substantially flexible logic integrated circuit contains testing circuitry, further comprising using the testing circuitry for testing circuits on at least one other of the at least one logic integrated circuit and the at least one thinned substantially flexible logic integrated circuit.

137. The method of claim 128, wherein at least one of the at least one logic integrated circuit and the at least one thinned substantially flexible logic integrated circuit contains at least one of a microprocessor, a graphics processor, a power management control circuitry and a content-addressable memory circuitry.

138. The method of claim 128, further comprising performing at least one of audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, ECC, logical to real address translation, graphical processing and database management processing.

197. The method of claim 128, further comprising forming the vertical connections from at least one of the front surface and back surface of the at least one thinned substantially flexible logic integrated circuit.

198. The method of claim 128, further comprising forming the vertical connections from the front surface of the at least one thinned substantially flexible logic integrated circuit.

199. The method of claim 198, further comprising thinning the at least one thinned substantially flexible logic integrated circuit until the vertical connections formed from the front surface are visible from the back surface.

200. The method of claim 198, further comprising thinning the at least one thinned substantially flexible logic integrated circuit, wherein the physical appearance on the back surface of the vertical connections formed from the front surface is used to control the thinning of the at least one thinned substantially flexible logic integrated circuit.

215. The method of claim 128, wherein at least one of the at least one logic integrated circuit and the at least one thinned substantially flexible logic integrated circuit is formed with a low stress dielectric, wherein the low stress dielectric is at least one of a silicon dioxide dielectric, an oxide of silicon dielectric and caused to have stress of about 5×

10⁸ dynes/cm² or less.

216. The method of claim 215, wherein the stress of the low stress dielectric is tensile.

218. The method of claim 216, wherein the stress of the low stress dielectric is tensile.

139. A method of using integrated circuitry having a data source formed in a first circuit layer, a data sink formed in a second circuit layer with a major portion of each of said first circuit layer and said second circuit layer held in unmovable relation to one another, and interconnect circuitry formed within a volume within which the first and second circuit layers overlie one another, the method comprising:

transferring control signals between the data source and the data sink; and

transferring a plurality of data bytes simultaneously between the data source and data sink.

140. The method of claim 139, wherein the interconnect circuitry connecting the data source and the data sink are vertical interconnections internal to the integrated circuitry.

141. The method of claim 139, wherein the data source and the data sink are made from one of a single crystal semiconductor material and polycrystalline semiconductor material.

142. The method of claim 139, wherein the data source and the data sink are made from at least one of active circuit devices and passive circuit devices.

143. The method of claim 139, wherein at least one of the data source and the data sink are made from a plurality of circuit layers with active devices.

144. The method of claim 139, wherein at least one of the data source and the data sink is caused to have a thickness of less than about 50 microns.

145. The method of claim 139, wherein at least one of the data source and the data sink is caused to have a thickness of less than about 10 microns.

146. The method of claim 139, wherein one of the data source and the data sink is made using a different process technology from one of the other the data source and the data sink.

147. The method of claim 146, wherein the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EEPROM, EPROM, Ferroelectric and Giant Magneto Resistance.

148. The method of claim 139, further comprising performing two or more simultaneous and independent data transfers between the data source and the data sink.

149. The method of claim 139, wherein the data source and the data sink are logic integrated circuits, further comprising the transfer of a plurality of data bytes between the logic integrated circuits.

150. The method of claim 139, wherein at least one of the data source and the data sink contains testing circuitry, further comprising using the testing circuitry for testing circuits on at least one other of the data source and the data sink.

151. The method of claim 139, wherein at least one of the data source and the data sink contains at least one of a microprocessor, a graphics processor, a power management control circuitry and a content-addressable memory circuitry.

152. The method of claim 139, further comprising performing at least one of audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, ECC, logical to real address translation, graphical processing and database management processing.

153. The method of claim 139, wherein one of the data source and the data sink is a memory controller circuit and one of the data source and the data sink is a memory circuit, further comprising the transfer of a plurality of data bytes between the memory controller circuit and the memory circuit.

154. The method of claim 153, wherein the memory controller circuit performs programmable gate line address assignment of internal circuitry with respect to the memory circuit.

155. The method of claim 153, further comprising:

the memory controller circuit testing the memory circuit to identify faulty memory locations; and

configuring the memory controller circuit by changing an address mapping within the memory controller circuit to the memory circuit such that at least one address previously mapped to a faulty memory location can be mapped away from the faulty memory location.

156. The method of claim 155, wherein at least one address previously mapped to a faulty memory location is mapped instead to an existing functional memory location.

157. The method of claim 155, wherein at least one address previously mapped to a faulty memory location is mapped instead to a null, non-existent memory location.

180. The method of claim 139, wherein one of the first circuit layer and the second circuit layer is a thinned substantially flexible circuit layer.

217. The method of claim 139, wherein at least one of the first circuit layer and the second circuit layer is formed with a low stress dielectric, wherein the low stress dielectric is at least one of a silicon dioxide dielectric, an oxide of silicon dielectric and caused to have stress of about 5×

10⁸ dynes/cm² or less.

158. A method of using integrated circuitry having a data source formed in a first circuit layer, a data sink formed in a second substantially flexible circuit layer, the first and second circuit layers substantially overlying each other with a major portion of each of said first circuit layer and said second substantially flexible circuit layer held in unmovable relation to one another and interconnect circuitry formed interconnecting the first and second circuit layers, the method comprising:

transferring control signals between the data source and the data sink; and

transferring a plurality of data bytes simultaneously between the data source and data sink.

159. The method of claim 158, wherein the interconnect circuitry connecting the data source and the data sink are vertical interconnections internal to the integrated circuitry.

160. The method of claim 158, wherein the interconnect circuitry connecting the data source and the data sink are vertical interconnections external to the integrated circuitry.

161. The method of claim 158, wherein the data source and the data sink are made from one of a single crystal semiconductor material and polycrystalline semiconductor material.

162. The method of claim 158, wherein the data source and the data sink are made from at least one of active circuit devices and passive circuit devices.

163. The method of claim 158, wherein at least one of the data source and the data sink are made from a plurality of circuit layers with active devices.

164. The method of claim 158, wherein at least one of the data source and the data sink is caused to have a thickness of less than about 50 microns.

165. The method of claim 158, wherein at least one of the data source and the data sink is caused to have a thickness of less than about 10 microns.

166. The method of claim 158, wherein one of the data source and the data sink is made using a different process technology from one of the other the data source and the data sink.

167. The method of claim 166, wherein the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EEPROM, EPROM, Ferroelectric and Giant Magneto Resistance.

168. The method of claim 158, further comprising performing two or more simultaneous and independent data transfers between the data source and the data sink.

169. The method of claim 158, wherein the data source and the data sink are logic integrated circuits, further comprising the transfer of a plurality of data bytes between the logic integrated circuits.

170. The method of claim 158, wherein at least one of the data source and the data sink contains testing circuitry, further comprising using the testing circuitry for testing circuits on at least one other of the data source and the data sink.

171. The method of claim 158, wherein at least one of the data source and the data sink contains at least one of a microprocessor, a graphics processor, a power management control circuitry and a content-addressable memory circuitry.

172. The method of claim 158, further comprising performing at least one of audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, ECC, logical to real address translation, graphical processing and database management processing.

173. The method of claim 158, wherein one of the data source and the data sink is a memory controller circuit and one of the data source and the data sink is a memory circuit, further comprising the transfer of a plurality of data bytes between the memory controller circuit and the memory circuit.

174. The method of claim 173, wherein the memory controller circuit performs programmable gate line address assignment of internal circuitry with respect to the memory circuit.

175. The method of claim 173, further comprising:

the memory controller circuit testing the memory circuit to identify faulty memory locations; and

configuring the memory controller circuit by changing an address mapping within the memory controller circuit to the memory circuit such that at least one address previously mapped to a faulty memory location can be mapped away from the faulty memory location.

176. The method of claim 175, wherein at least one address previously mapped to a faulty memory location is mapped instead to an existing functional memory location.

177. The method of claim 175, wherein at least one address previously mapped to a faulty memory location is mapped instead to a null, non-existent memory location.

219. The method of claim 158, wherein at least one of the first circuit layer and the second substantially flexible circuit layer is formed with a low stress dielectric, wherein the low stress dielectric is at least one of a silicon dioxide dielectric, an oxide of silicon dielectric and caused to have stress of about 5×

10⁸ dynes/cm² or less.

220. The method of claim 219, wherein the stress of the low stress dielectric is tensile.