Integration of biaxial tensile strained NMOS and uniaxial compressive strained PMOS on the same wafer
First Claim
1. A method of fabricating a biaxial tensile strained layer for NMOS fabrication and a uniaxial compression strained layer for PMOS fabrication on a single wafer for use in CMOS ICs, comprising:
- preparing a wafer, including preparing a silicon substrate for a CMOS device fabrication;
depositing, patterning and etching a first insulating layer on the silicon substrate;
depositing, patterning and etching a second insulating layer on the first insulating layer;
removing a portion of the second insulating layer from a PMOS active area;
depositing a layer of epitaxial silicon on the PMOS active area;
removing a portion of the second insulating layer from an NMOS active area;
growing an epitaxial silicon layer and growing an epitaxial SiGe layer on the NMOS active area;
implanting H2+ ions;
annealing the wafer to relax the SiGe layer;
removing the remaining second insulating layer;
smoothing the wafer by CMP;
growing a layer of silicon;
finishing a gate module;
depositing a layer of SiO2 over the NMOS active area;
etching silicon in the PMOS active area;
selectively growing a SiGe layer on the PMOS active area;
wherein the silicon layer in the NMOS active area is under biaxial tensile strain, and the silicon layer in the PMOS active area is uniaxial compression strained; and
completing the CMOS device.
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Abstract
A method of fabricating a biaxial tensile strained layer for NMOS fabrication and a uniaxial compressive strained layer for PMOS fabrication on a single wafer for use in CMOS ICs, includes preparing a silicon substrate for CMOS fabrication; depositing, patterning and etching a first and second insulating layers; removing a portion of the second insulating layer from a PMOS active area; depositing a layer of epitaxial silicon on the PMOS active area; removing a portion of the second insulating layer from an NMOS active area; growing an epitaxial silicon layer and growing an epitaxial SiGe layer on the NMOS active area; implanting H2+ ions; annealing the wafer to relax the SiGe layer; removing the remaining second insulating layer from the wafer; growing a layer of silicon; finishing a gate module; depositing a layer of SiO2 to cover the NMOS wafer; etching silicon in the PMOS active area; selectively growing a SiGe layer on the PMOS active area; wherein the silicon layer in the NMOS active area is under biaxial tensile strain, and the silicon layer in the PMOS active area is uniaxial compressive strained; and completing the CMOS device.
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Citations
12 Claims
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1. A method of fabricating a biaxial tensile strained layer for NMOS fabrication and a uniaxial compression strained layer for PMOS fabrication on a single wafer for use in CMOS ICs, comprising:
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preparing a wafer, including preparing a silicon substrate for a CMOS device fabrication; depositing, patterning and etching a first insulating layer on the silicon substrate; depositing, patterning and etching a second insulating layer on the first insulating layer; removing a portion of the second insulating layer from a PMOS active area; depositing a layer of epitaxial silicon on the PMOS active area; removing a portion of the second insulating layer from an NMOS active area; growing an epitaxial silicon layer and growing an epitaxial SiGe layer on the NMOS active area; implanting H2+ ions; annealing the wafer to relax the SiGe layer; removing the remaining second insulating layer; smoothing the wafer by CMP; growing a layer of silicon; finishing a gate module; depositing a layer of SiO2 over the NMOS active area; etching silicon in the PMOS active area; selectively growing a SiGe layer on the PMOS active area;
wherein the silicon layer in the NMOS active area is under biaxial tensile strain, and the silicon layer in the PMOS active area is uniaxial compression strained; andcompleting the CMOS device. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method of fabricating a biaxial tensile strained layer for NMOS fabrication and a uniaxial compression strained layer for PMOS fabrication on a silicon-on-insulator (SOI) wafer for use in CMOS ICs, comprising:
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preparing a silicon substrate as a donor wafer for SOI fabrication; depositing, patterning and etching a first insulating layer; depositing, patterning and etching a second insulating layer; removing a portion of the second insulating layer from a PMOS active area; depositing a layer of epitaxial silicon on the PMOS active area; removing a portion of the second insulating layer from an NMOS active area; growing an epitaxial SiGe layer on the NMOS active area; implanting H2+ ions; annealing the donor wafer to relax the SiGe layer; removing the remaining second insulating layer from the CMOS wafer; smoothing the donor wafer by CMP; selectively growing a layer of SiGe; selectively growing a layer of silicon; implanting a second dose of H2+ ions; preparing a silicon handle wafer; growing a layer of SiO2 on the silicon handle wafer; bonding the donor wafer to the silicon handle wafer to form a bonded pair; curing the bonded pair; splitting the bonded pair, thereby transferring a surface layer of the donar wafer to the silicon handle wafer; thinning the transferred surface layer to expose the SiGe layer; selectively removing SiGe; forming a gate dielectric, a gate and spacers; selectively growing an epitaxial SiGe layer on a PMOS source, a PMOS drain and PMOS gate; selectively growing an epitaxial silicon layer on a NMOS source, a NMOS drain and NMOS gate; annealing the NMOS/PMOS portion; wherein the silicon layer in the NMOS active area is under biaxial tensile strain, and the silicon layer in the PMOS active area is uniaxial compression strained; and completing the CMOS device. - View Dependent Claims (8, 9, 10, 11, 12)
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Specification