×

Integration of biaxial tensile strained NMOS and uniaxial compressive strained PMOS on the same wafer

  • US 7,138,309 B2
  • Filed: 01/19/2005
  • Issued: 11/21/2006
  • Est. Priority Date: 01/19/2005
  • Status: Active Grant
First Claim
Patent Images

1. A method of fabricating a biaxial tensile strained layer for NMOS fabrication and a uniaxial compression strained layer for PMOS fabrication on a single wafer for use in CMOS ICs, comprising:

  • preparing a wafer, including preparing a silicon substrate for a CMOS device fabrication;

    depositing, patterning and etching a first insulating layer on the silicon substrate;

    depositing, patterning and etching a second insulating layer on the first insulating layer;

    removing a portion of the second insulating layer from a PMOS active area;

    depositing a layer of epitaxial silicon on the PMOS active area;

    removing a portion of the second insulating layer from an NMOS active area;

    growing an epitaxial silicon layer and growing an epitaxial SiGe layer on the NMOS active area;

    implanting H2+ ions;

    annealing the wafer to relax the SiGe layer;

    removing the remaining second insulating layer;

    smoothing the wafer by CMP;

    growing a layer of silicon;

    finishing a gate module;

    depositing a layer of SiO2 over the NMOS active area;

    etching silicon in the PMOS active area;

    selectively growing a SiGe layer on the PMOS active area;

    wherein the silicon layer in the NMOS active area is under biaxial tensile strain, and the silicon layer in the PMOS active area is uniaxial compression strained; and

    completing the CMOS device.

View all claims
  • 2 Assignments
Timeline View
Assignment View
    ×
    ×