Integration of biaxial tensile strained NMOS and uniaxial compressive strained PMOS on the same wafer

• US 7,138,309 B2
• Filed: 01/19/2005
• Issued: 11/21/2006
• Est. Priority Date: 01/19/2005
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Laboratories of America Incorporated (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Maa, Jer-Shen, Lee, Jong-Jan, Hsu, Sheng Teng, Tweet, Douglas J.
• Primary Examiner(s): LINDSAY JR, WALTER LEE
• Application Number:
  US11/039,542
• Publication Number:
  US 20060160291A1
• Time in Patent Office: 671 Days
• Field of Search: 438/197, 438/199, 438/233, 438/231, 438/758, 438/300, 438/296, 257/E21.129, 257/E21.431
• US Class Current: 438/197
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054

Abstract

A method of fabricating a biaxial tensile strained layer for NMOS fabrication and a uniaxial compressive strained layer for PMOS fabrication on a single wafer for use in CMOS ICs, includes preparing a silicon substrate for CMOS fabrication; depositing, patterning and etching a first and second insulating layers; removing a portion of the second insulating layer from a PMOS active area; depositing a layer of epitaxial silicon on the PMOS active area; removing a portion of the second insulating layer from an NMOS active area; growing an epitaxial silicon layer and growing an epitaxial SiGe layer on the NMOS active area; implanting H₂⁺ ions; annealing the wafer to relax the SiGe layer; removing the remaining second insulating layer from the wafer; growing a layer of silicon; finishing a gate module; depositing a layer of SiO₂ to cover the NMOS wafer; etching silicon in the PMOS active area; selectively growing a SiGe layer on the PMOS active area; wherein the silicon layer in the NMOS active area is under biaxial tensile strain, and the silicon layer in the PMOS active area is uniaxial compressive strained; and completing the CMOS device.

Claims

1. A method of fabricating a biaxial tensile strained layer for NMOS fabrication and a uniaxial compression strained layer for PMOS fabrication on a single wafer for use in CMOS ICs, comprising:

preparing a wafer, including preparing a silicon substrate for a CMOS device fabrication;

depositing, patterning and etching a first insulating layer on the silicon substrate;

depositing, patterning and etching a second insulating layer on the first insulating layer;

removing a portion of the second insulating layer from a PMOS active area;

depositing a layer of epitaxial silicon on the PMOS active area;

removing a portion of the second insulating layer from an NMOS active area;

growing an epitaxial silicon layer and growing an epitaxial SiGe layer on the NMOS active area;

implanting H₂⁺ ions;

annealing the wafer to relax the SiGe layer;

removing the remaining second insulating layer;

smoothing the wafer by CMP;

growing a layer of silicon;

finishing a gate module;

depositing a layer of SiO₂ over the NMOS active area;

etching silicon in the PMOS active area;

selectively growing a SiGe layer on the PMOS active area;

wherein the silicon layer in the NMOS active area is under biaxial tensile strain, and the silicon layer in the PMOS active area is uniaxial compression strained; and

completing the CMOS device.

2. The method of claim 1 wherein a first insulating layer is taken from the group of dielectric materials consisting of Si₃N₄ and SiO₂, and wherein a second insulating layer is taken from the group of dielectric materials consisting of SiO₂ and Si₃N₄, and wherein the first insulating layer material is different than the second insulating layer material.

3. The method of claim 1 wherein said growing an epitaxial silicon layer and growing an epitaxial SiGe layer on the NMOS active area includes growing the SiGe layer at a temperature of between about 400°

C. to 700°

C. to prevent relaxation of the SiGe lattice.

4. The method of claim 3 wherein said growing an epitaxial silicon layer and growing an epitaxial SiGe layer on the NMOS active area includes growing the epitaxial silicon layer and the epitaxial SiGe layer to a combined thickness which is 10 nm to 100 nm thicker than the thickness of the first insulating layer.

5. The method of claim 1 wherein said growing an epitaxial silicon layer and growing an epitaxial SiGe layer on the NMOS active area includes growing the epitaxial SiGe layer with a larger lattice constant than that of the underlying epitaxial silicon layer, resulting in the epitaxial SiGe under biaxial compressive strain.

6. The method of claim 1 where said implanting H₂⁺ ions includes implanting H₂⁺ ions at a dose of between about 5×

10¹⁵ cm<sup>−

2</sup> to 3×

10¹⁶ cm<sup>−

2</sup> and at an implantation energy of between about 30 keV to 100 keV, to have a projected ion penetration range (Rp) equal or between about 10 nm to 50 nm greater than the SiGe thickness.

7. A method of fabricating a biaxial tensile strained layer for NMOS fabrication and a uniaxial compression strained layer for PMOS fabrication on a silicon-on-insulator (SOI) wafer for use in CMOS ICs, comprising:

preparing a silicon substrate as a donor wafer for SOI fabrication;

depositing, patterning and etching a first insulating layer;

depositing, patterning and etching a second insulating layer;

removing a portion of the second insulating layer from a PMOS active area;

depositing a layer of epitaxial silicon on the PMOS active area;

removing a portion of the second insulating layer from an NMOS active area;

growing an epitaxial SiGe layer on the NMOS active area;

implanting H₂⁺ ions;

annealing the donor wafer to relax the SiGe layer;

removing the remaining second insulating layer from the CMOS wafer;

smoothing the donor wafer by CMP;

selectively growing a layer of SiGe;

selectively growing a layer of silicon;

implanting a second dose of H₂⁺ ions;

preparing a silicon handle wafer;

growing a layer of SiO₂ on the silicon handle wafer;

bonding the donor wafer to the silicon handle wafer to form a bonded pair;

curing the bonded pair;

splitting the bonded pair, thereby transferring a surface layer of the donar wafer to the silicon handle wafer;

thinning the transferred surface layer to expose the SiGe layer;

selectively removing SiGe;

forming a gate dielectric, a gate and spacers;

selectively growing an epitaxial SiGe layer on a PMOS source, a PMOS drain and PMOS gate;

selectively growing an epitaxial silicon layer on a NMOS source, a NMOS drain and NMOS gate;

annealing the NMOS/PMOS portion;

wherein the silicon layer in the NMOS active area is under biaxial tensile strain, and the silicon layer in the PMOS active area is uniaxial compression strained; and

completing the CMOS device.

8. The method of claim 7 wherein a first insulating layer is taken from the group of dielectric materials consisting of Si₃N₄ and SiO₂, and wherein a second insulating layer is taken from the group of dielectric materials consisting of SiO₂ and Si₃N₄, and wherein the first insulating layer material is different than the second insulating layer material.

9. The method of claim 7 wherein said growing an epitaxial SiGe layer on the NMOS active area includes growing the SiGe layer at a temperature of between about 400°

C. to 700°

C. to prevent relaxation of the SiGe lattice.

10. The method of claim 9 wherein said growing an epitaxial SiGe layer on the NMOS active area which is 10 nm to 100 nm thicker than the thickness of the first insulating layer.

11. The method of claim 7 wherein said growing an epitaxial SiGe layer with a larger lattice constant than that of the underlying silicon substrate, resulting in the epitaxial SiGe under biaxial compressive strain.

12. The method of claim 7 where said implanting H₂⁺ ions includes implanting H₂⁺ ions at a dose of between about 5×

10¹⁵ cm<sup>−

2</sup> to 3×

10¹⁶ cm<sup>−

2</sup> and at an implantation energy of between about 30 keV to 100 keV, to have a projected ion penetration range (Rp) equal or between about 10 nm to 50 nm greater than the SiGe thickness.