Thin film transistor array panel including symmetrically aligned thin film transistors and manufacturing method thereof

• US 7,138,655 B2
• Filed: 11/20/2003
• Issued: 11/21/2006
• Est. Priority Date: 11/20/2002
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Tak, Young-Mi, Kim, Dong-Gyu, Baek, Seung-Soo, Youn, Joo-Ae
• Primary Examiner(s): PHAM, HOAI V
• Application Number:
  US10/718,309
• Publication Number:
  US 20040099865A1
• Time in Patent Office: 1,097 Days
• Field of Search: 257/59, 257/72, 257/347, 257/350, 257/351, 257/352, 257/353
• US Class Current: 257/59
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A TFT array panel includes: first and second gate members connected to each other; a gate insulating layer formed on the first and the second gate members; first and second semiconductor members formed on the gate insulating layer opposite the first and the second gate members, respectively; first and second source members connected to each other and located near the first and the second semiconductor members, respectively; first and second drain members located near the first and the second semiconductor members, respectively, and located opposite the first and the second source members with respect to the first and the second gate members, respectively; and a pixel electrode connected to the first and the second drain members. The first gate, semiconductor, source, and drain members form a first TFT, and the second gate, semiconductor, source, and drain members form a second TFT.

Claims

1. A thin film transistor array panel comprising:

first and second gate members connected to each other;

a gate insulating layer formed on the first and the second gate members;

first and second semiconductor members formed on the gate insulating layer, respectively;

first and second source members connected to each other and located near the first and the second semiconductor members, respectively;

first and second drain members located near the first and the second semiconductor members, respectively, and located opposite the first and the second source members, respectively; and

a pixel electrode connected to the first and the second drain members, wherein the first gate member, the first semiconductor member, the first source member, and the first drain members form a first thin film transistor, and the second gate member, the second semiconductor member, the second source member, and the second drain members form a second thin film transistor.

2. The thin film transistor array panel of claim 1, wherein the first thin film transistor and the second thin film transistor are symmetrically aligned.

3. The thin film transistor array panel of claim 2, wherein the alignment of the first and the second thin film transistors are symmetrical with respect to a predetermined line.

4. The thin film transistor array panel of claim 3, wherein the predetermined line includes a boundary line between shots in light exposure.

5. The thin film transistor array panel of claim 4, further comprising a third thin film transistor different from the first and the second thin film transistors.

6. The thin film transistor array panel of claim 1, wherein the alignment of the first and the second thin film transistors are located opposite each other with respect to a boundary line between shots in light exposure.

7. The thin film transistor array panel of claim 1, wherein channels of the first and the second thin film transistors have curved shapes.

8. The thin film transistor array panel of claim 7, wherein channels of the first and the second thin film transistors have U or C shapes.

9. The thin film transistor array panel of claim 1, wherein the first and the second semiconductor members have substantially the same planar shapes as the first and the second source and drain members except for channel portions of the first and the second thin film transistors.

10. A thin film transistor array panel comprising:

first and second gate members connected to each other;

a gate insulating layer formed on the first and the second gate members;

first and second semiconductor members formed on the gate insulating layer;

first and second source members connected to each other and located over the first and the second semiconductor members, respectively;

first and second drain members located over the first and the second semiconductor members, respectively, and located opposite the first and the second source members, respectively; and

a pixel electrode connected to the first and the second drain members,

wherein the first gate member, the first semiconductor member, the first source member, and the first drain members form a first thin film transistor, and the second gate member, the second semiconductor member, the second source member, and the second drain members form a second thin film transistor.

11. The thin film transistor array panel of claim 10, wherein the first thin film transistor and the second thin film transistor are symmetrically aligned.

12. The thin film transistor array panel of claim 11, wherein the alignment at the first and the second thin film transistors are symmetrical with respect to a predetermined line.

13. The thin film transistor array panel of claim 12, wherein the predetermined line includes a boundary line between shots in light exposure.

14. The thin film transistor array panel of claim 13, further comprising a third thin film transistor different from the first and the second thin film transistors.

15. The thin film transistor array panel of claim 10, wherein the alignment of the first and the second thin film transistors are located opposite each other with respect to a boundary line between shots in light exposure.

16. The thin film transistor array panel of claim 10, wherein channels of the first and the second thin film transistors have curved shapes.

17. The thin film transistor array panel of claim 16, wherein channels of the first and the second thin film transistors have U or C shapes.

18. The thin film transistor array panel of claim 10, wherein the first and the second semiconductor members have substantially the same planar shapes a the first and the second source and drain members except for channel portions of the first and the second thin film transistors.