Heterojunction diode with reduced leakage current

• US 7,138,668 B2
• Filed: 07/26/2004
• Issued: 11/21/2006
• Est. Priority Date: 07/30/2003
• Status: Active Grant

• Current Assignee: Nissan Motor Co., Ltd.
• Original Assignee: Nissan Motor Co., Ltd.
• Inventors: Tanaka, Hideaki, Hoshi, Masakatsu, Hayashi, Tetsuya, Kaneko, Saichirou
• Primary Examiner(s): Flynn, Nathan J.
• Assistant Examiner(s): Wilson, Scott R.
• Application Number:
  US10/898,224
• Publication Number:
  US 20050045892A1
• Time in Patent Office: 848 Days
• Field of Search: None
• US Class Current: 257/183
• CPC Class Codes: H01L 21/046 using ion implantation
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7805 in antiparallel, e.g. freewheel diode
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: H01L 29/8083 Vertical transistors SIT H01L29/7722
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

An aspect of the present invention provides a semiconductor device that includes a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type, having a different band gap from the first semiconductor region and forming a heterojunction with the first semiconductor region.

Claims

1. A semiconductor device comprising:

a first semiconductor region of a first conductivity type; and

a second semiconductor region of a second conductivity type, having a different band gap from the first semiconductor region and forming a heterojunction with the first semiconductor region,

wherein the second semiconductor region includes a non-depletion area that is not depleted when a reverse bias is applied to the heterodiode,

wherein the thickness of the non-depletion area that is not depleted when a reverse bias is applied to the heterodiode is greater than a diffusion length in the non-depletion area of carriers that act as majority carriers in the first semiconductor region.

2. The semiconductor device of claim 1 wherein:

the non-depletion area has an impurity concentration equal to or greater than an impurity concentration of the first semiconductor region.

3. The semiconductor device of claim 1, wherein:

a principal ingredient of the first semiconductor region is silicon carbide.

4. The semiconductor device of claim 1, wherein:

the second semiconductor region is made of a material selected from the group consisting of monocrystalline silicon, amorphous silicon, and polysilicon.

5. The semiconductor device of claim 1, further comprising:

a semiconductor base including the first semiconductor region;

an anode electrode formed in contact with a first principal face of the semiconductor base;

a cathode electrode in contact with an opposite face of the semiconductor base, the opposite face opposing the first principal face; and

at least one electric field relaxation region containing impurities, formed in the first semiconductor region in contact with the heterojunction.

6. The semiconductor device of claim 5, wherein:

the electric field relaxation region is arranged in an annular shape around the anode electrode.

7. The semiconductor device of claim 5, wherein:

a plurality of the electric field relaxation regions are arranged at predetermined intervals.

8. The semiconductor device of claim 1, further comprising:

an active region including;

a drain region formed in a semiconductor base that includes the first semiconductor region;

a source region formed in the second semiconductor region that has a different band gap from the first semiconductor region; and

a drive region;

a gate electrode;

a gate insulating film to insulate the gate electrode from the semiconductor base and source region;

a drain electrode formed in contact with the drain region;

a source electrode formed in contact with the source region; and

at least one electric field relaxation region with impurities introduced therein, formed in the first semiconductor region in contact with the heterojunction.

9. The semiconductor device of claim 8, wherein:

at least one electric field relaxation region is arranged inside of the active region.

10. The semiconductor device of claim 8, further comprising:

a trench formed on a first principal face of the semiconductor base.

11. A semiconductor device comprising:

a first semiconductor region of a first conductivity type; and

a second semiconductor region of a second conductivity type, having a different band gap from the first semiconductor region and forming a heterojunction with the first semiconductor region,

wherein the second semiconductor region includes a non-depletion area that is not depleted when a reverse bias is applied to the heterodiode,

wherein the non-depletion area has an impurity concentration that is higher than an impurity concentration of the first semiconductor region by a critical-field-strength ratio of the first semiconductor region to the second semiconductor region.

12. A semiconductor device comprising:

a first semiconductor region of a first conductivity type;

a second semiconductor region of a second conductivity type, having a different band gap from the first semiconductor region and forming a heterojunction with the first semiconductor region;

a semiconductor base including the first semiconductor region;

a hetero-semiconductor region that is in contact with a principal face of the semiconductor base and has a different band gap from the semiconductor base, at least part of the hetero-semiconductor region being the second semiconductor region;

a gate insulating film formed in contact with a part of a junction between the hetero-semiconductor region and the semiconductor base; and

a gate electrode insulated by the gate insulating film from the hetero-semiconductor region and the semiconductor base.

13. The semiconductor device of claim 12, further comprising:

a base region of the second conductivity type formed in the semiconductor base; and

a source region of the first conductivity type formed in the semiconductor base.

14. A semiconductor device comprising:

a first semiconductor region of a first conductivity type;

a second semiconductor region of a second conductivity type, having a different band gap from the first semiconductor region and forming a heterojunction with the first semiconductor region;

an electric field relaxation region of the second conductivity type with impurities introduced therein, formed in the first semiconductor region in contact with the heterojunction; and

a punch-through preventive region of the second conductivity type formed in the first semiconductor region in contact with a junction face between the first semiconductor region and the second semiconductor region, an impurity concentration of the punch-through preventive region being equal to or greater than an impurity concentration of the electric field relaxation region.

15. The semiconductor device of claim 14, wherein:

an end of the second semiconductor region in contact with the first semiconductor region is of the second conductivity type.

16. The semiconductor device of claim 14, wherein:

an end of the second semiconductor region in contact with the first semiconductor region is ohmic-connected to the punch-through preventive region.

17. The semiconductor device of claim 14, wherein:

the second semiconductor region, punch-through preventive region, and electric field relaxation region are formed in the vicinity of an outermost periphery of a junction between the heterojunction and a semiconductor base that includes the first semiconductor region.

18. The semiconductor device of claim 14, further comprising:

a gate insulating film and a gate electrode formed at a part of a junction between the second semiconductor region or hetero-semiconductor region and a semiconductor base that includes the first semiconductor region.

19. The semiconductor device of claim 14, further comprising:

a semiconductor base including the first semiconductor region;

a base region of the second conductivity type formed in a predetermined area of the semiconductor base;

a source region of the first conductivity type formed in a predetermined area of the semiconductor base;

a gate insulating film formed in contact with a part of a junction between the hetero-semiconductor region and the semiconductor base;

a gate electrode insulated by the gate insulating film from the hetero-semiconductor region and the semiconductor base; and

a gate electrode and a gate insulating film formed in contact with the semiconductor base and source region,

wherein the electric field relaxation region and punch-through preventive region is formed in the vicinity of an outermost periphery of a junction between the semiconductor base and the second semiconductor region.

20. A method of manufacturing a semiconductor device, comprising:

forming a first semiconductor region from a first semiconductor material;

forming a second semiconductor region on a surface of the first semiconductor region from a second semiconductor material whose band gap is different from that of the first semiconductor material, thereby forming a heterojunction between the first semiconductor region and the second semiconductor region; and

introducing impurities into a surface of the first semiconductor region over the second semiconductor region, to form an electric field relaxation region in the first semiconductor region that forms the heterojunction with the second semiconductor region.

21. The method of claim 20, wherein:

the introducing impurities into a surface of the second semiconductor region is conducted by ion implantation.

22. The method of claim 20, wherein:

the second semiconductor region is partly or wholly formed to be thinner than a flying distance of the impurities to be introduced.