Semiconductor device

• US 7,138,692 B2
• Filed: 12/17/2004
• Issued: 11/21/2006
• Est. Priority Date: 06/14/2004
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Sasaki, Takaoki, Tamura, Yasuyuki
• Primary Examiner(s): Jackson, Jerome
• Assistant Examiner(s): DIAZ, JOSE R
• Application Number:
  US11/013,541
• Publication Number:
  US 20050274948A1
• Time in Patent Office: 704 Days
• Field of Search: 257/412
• US Class Current: 257/412
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/2822 with substrate doping, e.g. N, Ge, C implantation, before formation of the insulator
• CPC Class Codes: H01L 21/28238 with sacrificial oxide
• CPC Class Codes: H01L 29/512 the variation being parallel to the channel plane
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

A gate insulating film and a gate electrode are formed on a silicon substrate. The gate insulating film contains at least hafnium, oxygen, fluorine, and nitrogen. The fluorine concentration is high in the vicinity of an interface with the silicon substrate and progressively decreases with decreasing distance from the gate electrode. The nitrogen concentration is high in the vicinity of an interface with the gate electrode and progressively decreases with decreasing distance from the silicon substrate. The fluorine concentration in the vicinity of the interface with the silicon substrate is preferably 1×10¹⁹ cm⁻³ or more. The nitrogen concentration in the vicinity of the interface with the gate electrode is preferably 1×10²⁰ cm⁻³ or more.

Claims

1. A semiconductor device comprising:

a silicon substrate;

a gate insulating film on said silicon substrate; and

a gate electrode on said gate insulating film, wherein

said gate insulating film contains at least hafnium, oxygen, fluorine, and nitrogen,

concentration of said fluorine in said gate insulating film is high proximate an interface with said silicon substrate and progressively decreases with decreasing distance from said gate electrode, and

concentration of said nitrogen in said gate insulating film is high proximate an interface with said gate electrode and progressively decreases with decreasing distance from said silicon substrate.

2. The semiconductor device as claimed in claim 1, wherein the concentration of said fluorine in said gate insulating film proximate said interface with said silicon substrate is at least 1×

10¹⁹ cm<sup>−

3</sup>.

3. The semiconductor device as claimed in claim 1, wherein the concentration of said nitrogen in said gate insulating film proximate said interface with said gate electrode is at least 1×

10²⁰ cm<sup>−

3</sup>.

4. A semiconductor device comprising:

a silicon substrate;

a gate insulating film on said silicon substrate; and

a gate electrode on said gate insulating film, wherein

said gate insulating film contains at least hafnium, oxygen, fluorine, and nitrogen, and

in regions of said gate insulating film other than proximate an interface with said silicon substrate, concentration of said nitrogen is higher than concentration of said fluorine.

5. The semiconductor device as claimed in claim 4, wherein said gate insulating film includes, proximate said interface with said silicon substrate, a region extending 1 nm–

1.5 nm from said interface in a thickness direction of said gate insulating film.