Multilevel interconnect structure with low-k dielectric

• US 7,138,718 B2
• Filed: 02/02/2004
• Issued: 11/21/2006
• Est. Priority Date: 06/13/1997
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ahn, Kie Y., Forbes, Leonard
• Primary Examiner(s): Cao, Phat X.
• Application Number:
  US10/768,019
• Publication Number:
  US 20040150109A1
• Time in Patent Office: 1,023 Days
• Field of Search: 257/758, 257/522, 257/762, 257/763, 257/637, 438/637
• US Class Current: 257/762
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A multilevel interconnect structure with a low-k dielectric constant is fabricated in an integrated circuit structure by the steps of depositing a layer of photoresist on a substrate assembly, etching the photoresist to form openings, forming a metal layer on the photoresist layer to fill the openings and then removing the photoresist layer by, for example, ashing. The metal layer is supported by the metal which filled the openings formed in the photoresist.

Claims

1. A semiconductor device comprising:

a substrate assembly; and

at least one interconnect structure on said substrate assembly, said interconnect structure comprising;

a first metal plug formed above and in electrical contact with said substrate assembly;

a metal layer having a portion elevated above said substrate assembly and a portion defining a second metal plug formed below said elevated portion of said metal layer and in electrical contact with said first metal plug, said first and second metal plugs supporting said elevated portion of said metal layer, wherein said first and second metal plugs and said metal layer are formed of a copper containing material;

a diffusion barrier layer of TiN provided over said metal layer;

a bilayer adhesion promoter/diffusion barrier provided under at least one of the first and second metal plugs, said bilayer adhesion promoter/diffusion barrier formed of a group consisting of titanium/copper, chromium/copper, titanium nitride/copper, tantalum/copper, W/copper and WN/copper;

a gas surrounding said first and second metal plugs; and

a low-k dielectric film over said metal layer and said diffusion barrier layer of TiN.

2. The semiconductor device of claim 1 wherein said gas is air.

3. A semiconductor device of claim 1 wherein said low-k dielectric film has a dielectric constant of about 1 to about 2.5.

4. A semiconductor device of claim 3 wherein said low-k dielectric film has a dielectric constant of about 1 to 2.0.

5. A semiconductor device of claim 1 wherein said low-k dielectric film comprises one of an aerogel and a xerogel.

6. A semiconductor device of claim 1 wherein said metal layer has a thickness of from about 0.5 micron to about 1.0 micron.

7. The semiconductor device of claim 1 further comprising a third metal plug formed between said first metal plug and said second metal plug.