Programmable phase shift and duty cycle correction circuit and method
First Claim
1. A circuit configured for generating an output signal in response to an input signal, the circuit comprising:
- a storage device configured for generating a linearly increasing voltage signal when charged;
series-coupled current source and switch further coupled in series with the storage device for charging the storage device when the switch is closed;
a programmable digital-to-analog converter (DAC) configured for generating an adjustable reference voltage;
a comparator having a pair of inputs, one coupled to the storage device and one to the programmable DAC, wherein the comparator is configured for transitioning the output signal from logic LOW to logic HIGH once the linearly increasing voltage exceeds the adjustable reference voltage, and wherein a phase difference between the input and output signals is determined, at least in part, by the adjustable reference voltage; and
a delay sub-circuit coupled for receiving the input signal and configured for generating a discharge signal on each rising edge of the input signal.
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Accused Products
Abstract
A phase shift and duty cycle correction circuit is disclosed herein as comprising a programmable digital to analog converter (DAC), a storage device (e.g., a capacitor), a charge sub-circuit and dump sub-circuit for charging and discharging the storage device, respectively, a comparator, and a clock driver circuit. A linearly increasing (or ramped) voltage waveform is generated within the storage device by the charging and discharging actions of the charge and dump sub-circuits; a periodic process which is controlled by opposite phases of the input clock. By programming the DAC control input to change the slicing threshold of the ramped waveform, the circuit and method described herein provides a means for programmable phase shifting and duty cycle correction.
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Citations
25 Claims
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1. A circuit configured for generating an output signal in response to an input signal, the circuit comprising:
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a storage device configured for generating a linearly increasing voltage signal when charged; series-coupled current source and switch further coupled in series with the storage device for charging the storage device when the switch is closed; a programmable digital-to-analog converter (DAC) configured for generating an adjustable reference voltage; a comparator having a pair of inputs, one coupled to the storage device and one to the programmable DAC, wherein the comparator is configured for transitioning the output signal from logic LOW to logic HIGH once the linearly increasing voltage exceeds the adjustable reference voltage, and wherein a phase difference between the input and output signals is determined, at least in part, by the adjustable reference voltage; and a delay sub-circuit coupled for receiving the input signal and configured for generating a discharge signal on each rising edge of the input signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A circuit configured for generating an output signal from a pair of complementary input signals, the circuit comprising:
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a first circuit block coupled for receiving a first one of the pair of complementary input signals, generating a first linearly increasing voltage in response to a rising edge of the first input signal, and transitioning the output signal from logic LOW to logic HIGH once the first linearly increasing voltage exceeds a first adjustable reference voltage set by the first circuit block; a second circuit block, substantially identical to the first circuit block, wherein the second circuit block is coupled for receiving a second one of the pair of complementary input signals, generating a second linearly increasing voltage in response to a rising edge the second input signal, and transitioning the output signal from logic HIGH to logic LOW once the second linearly increasing voltage exceeds a second adjustable reference voltage set by the second circuit block; and wherein at least one of the adjustable reference voltages set by the first and second circuit blocks can be adjusted to alter a duty cycle of the output signal and/or a phase difference between the input and output signals. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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19. A method for generating an output signal from a pair of complementary input signals, the method comprising:
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producing a first linearly increasing voltage signal upon receiving a rising edge of a first one of the pair of complementary input signals; generating a logic HIGH output signal once the first linearly increasing voltage signal exceeds a first adjustable reference voltage; producing a second linearly increasing voltage signal upon receiving a rising edge of a second one of the pair of complementary input signals; generating a logic LOW output signal once the second linearly increasing voltage signal exceeds a second adjustable reference voltage; and setting the first and second adjustable reference voltages to control a duty cycle and phase shift amount associated with the output signal. - View Dependent Claims (20, 21, 22, 23, 24, 25)
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Specification