Methods of processing graphics data including reading and writing buffers

• US 7,139,003 B1
• Filed: 12/15/2003
• Issued: 11/21/2006
• Est. Priority Date: 12/15/2003
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Moinar, Steven E., Papakipos, Matthew N., Bastos, Rui M., Lindholm, John Erik, Kirk, David B.
• Primary Examiner(s): Chauhan, Ulka
• Assistant Examiner(s): Hsu, Joni
• Application Number:
  US10/736,437
• Time in Patent Office: 1,072 Days
• Field of Search: 345/501, 345/506, 345/522, 345/531, 345/530, 345/557, 345/614, 345/418, 345/426, 345/564, 345/565
• US Class Current: 345/531
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/3856 Reordering of instructions, e.g. using queues or age tags
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory

Abstract

Apparatuses and methods for detecting position conflicts during fragment processing are described. Prior to executing a program on a fragment, a conflict detection unit, within a fragment processor checks if there is a position conflict indicating a RAW (read after write) hazard may exist. A RAW hazard exists when there is a pending write to a destination location that source data will be read from during execution of the program. When the fragment enters a processing pipeline, each destination location that may be written during the processing of the fragment is entered in conflict detection unit. During processing, the conflict detection unit is updated when a pending write to a destination location is completed.

Claims

1. A computer-readable medium that includes a set of instructions that when executed by a computing device causes the computing device to process fragment data in a fragment processing pipeline, by performing the steps of:

shading a first fragment associated with a destination location in a buffer;

storing the result of the first fragment shading in the destination location in the buffer;

shading a second fragment which is to be based in part on reading the result of the first fragment shading from the destination location;

detecting in a conflict detection unit that a read after write position conflict exists for the destination location in the buffer associated with the first and second fragments and interrupting the processing of second fragment;

outputting write position information to the conflict detection unit confirming that shading of the first fragment and writing to the buffer is complete; and

on completing processing of the first fragment and storing the result in the destination location in the buffer resuming processing of the second fragment, processing of the second fragment including reading the destination location in the buffer without an intervening instruction to flush the fragment processing pipeline.

2. The computer-readable medium of claim 1, wherein the destination location includes a buffer identifier corresponding to one of several buffers.

3. The computer-readable medium of claim 1 comprising fragment program instructions to configure the fragment processing pipeline to perform depth buffering prior to shading.

4. The computer-readable medium of claim 1, comprising fragment program instructions to configure the fragment processing pipeline to perform depth peeling.

5. The computer-readable medium of claim 1, comprising:

fragment program instructions to configure the fragment processing pipeline to perform raster operations.

6. The computer-readable medium of claim 1, wherein raster operations are performed using fragment data represented in a floating-point data format.

7. The computer-readable medium as claimed in claim 1, including processing one or more additional fragments following processing the first fragment without unlocking the second fragment.

8. A programmable graphics processor for execution of program instructions, comprising:

a read interface configured to read data from a graphics memory;

a fragment processing unit configured to receive fragments, each fragment associated with a position, and the data from the graphics memory and generate processed fragments;

a conflict detection unit configured to selectively store the position associated with each fragment and generate a position conflict status;

a write interface configured to write the processed fragments to the graphics memory; and

a fragment processing pipeline configured to handle read-after-write hazards during execution of shader programs including an instruction to write a location in graphics memory, an instruction to check the location in a conflict detection unit and a subsequent instruction to read a location in graphics memory without an intervening instruction to flush the fragment processing pipeline based on the check of the conflict detection unit.

9. The programmable graphics processor as claimed in claim 8, including a data cache storing additional data associated with the location, the conflict detection unit determining if the additional data associated with the location is available.

10. The programmable graphics processor as claimed in claim 9, wherein the location is a region comprising a plurality of pixels.