Memory cell array
First Claim
1. A memory cell array comprising:
- memory cells, each of the memory cells comprising a storage element and an access transistor;
bit lines running along a first direction;
word lines running along a second direction substantially perpendicular to the first direction; and
a semiconductor substrate, continuous active area lines and isolation trenches being formed in the semiconductor substrate, the isolation trenches being adjacent to the active area lines, and the isolation trenches being adapted to electrically isolate neighboring active area lines from each other, the access transistors being at least partially formed in the active area lines and electrically coupling corresponding storage elements to corresponding bit lines via bit line contacts, the transistors being addressed by the word lines;
wherein the bit line contacts are formed in a region generally defined by an intersection of a bit line and a corresponding active area line; and
wherein neighboring bit line contacts, each of which is connected to an active area line, are connected with neighboring bit lines.
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Accused Products
Abstract
A memory cell array includes memory cells, bit lines running along a first direction, word lines running along a second direction perpendicular to the first direction, and continuous active area lines, wherein transistors are at least partially formed in the active area lines. The transistors electrically couple corresponding memory cells to corresponding bit lines via bit line contacts, and the transistors are addressed by the word lines. The bit line contacts are formed in a region generally defined by an intersection of a bit line and a corresponding active area line. Neighboring bit line contacts which are connected with one active area line are connected with neighboring bit lines. Consequently, one active area line is crossed by a plurality of bit lines.
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Citations
21 Claims
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1. A memory cell array comprising:
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memory cells, each of the memory cells comprising a storage element and an access transistor; bit lines running along a first direction; word lines running along a second direction substantially perpendicular to the first direction; and a semiconductor substrate, continuous active area lines and isolation trenches being formed in the semiconductor substrate, the isolation trenches being adjacent to the active area lines, and the isolation trenches being adapted to electrically isolate neighboring active area lines from each other, the access transistors being at least partially formed in the active area lines and electrically coupling corresponding storage elements to corresponding bit lines via bit line contacts, the transistors being addressed by the word lines; wherein the bit line contacts are formed in a region generally defined by an intersection of a bit line and a corresponding active area line; and wherein neighboring bit line contacts, each of which is connected to an active area line, are connected with neighboring bit lines. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A memory cell array comprising:
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memory cells, each of the memory cells comprising a storage element and an access transistor; bit lines running along a first direction, the bit lines being formed as straight bit lines; and a semiconductor substrate, continuous active area lines and isolation trenches being formed in the semiconductor substrate, the isolation trenches being adjacent to the active area lines, and the isolation trenches being adapted to electrically isolate neighboring active area lines from each other, the access transistors being at least partially formed in the active area lines and electrically coupling corresponding storage elements to corresponding bit lines via bit line contacts, the access transistors being addressed by the word lines; wherein the bit line contacts are formed in a region generally defined by an intersection of a bit line and a corresponding active area line; and wherein neighboring bit line contacts, each of which is connected with an active area line, are connected with neighboring bit lines. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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Specification