Efficient verification for coarse/fine programming of non-volatile memory

• US 7,139,198 B2
• Filed: 01/27/2004
• Issued: 11/21/2006
• Est. Priority Date: 01/27/2004
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Mokhlesi, Nima, Guterman, Daniel C., Fong, Yupin
• Primary Examiner(s): HUR, JUNG H
• Application Number:
  US10/766,217
• Publication Number:
  US 20050162916A1
• Time in Patent Office: 1,029 Days
• Field of Search: 365/185.11, 365/185.21, 365/185.22, 365/230.03, 365/189.04, 365/185.03
• US Class Current: 365/185.22
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 16/3481 Circuits or methods to verify correct programming of nonvolatile memory cells whilst programming is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate programming
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 2211/5624 Concurrent multilevel programming and programming verification

Abstract

A non-volatile memory device is programmed by first performing a coarse programming process and subsequently performing a fine programming process. The coarse/fine programming methodology is enhanced by using an efficient verification scheme that allows some non-volatile memory cells to be verified for the coarse programming process while other non-volatile memory cells are verified for the fine programming process. The fine programming process can be accomplished using current sinking, charge packet metering or other suitable means.

Claims

1. An apparatus for programming non-volatile storage elements, comprising:

a programming circuit in communication with said non-volatile storage elements;

a common control line connected to said non-volatile storage elements and in communication with said programming circuit; and

one or more verification selection circuits in communication with said non-volatile storage elements, said one or more verification selection circuits cause a first subset of said non-volatile storage elements connected to said common control line to be subjected to coarse verification concurrently while a second subset of said non-volatile storage elements connected to said common control line are subjected to fine verification.

2. An apparatus according to claim 1, wherein:

said one or more verification selection circuits include one verification selection circuit for each non-volatile storage element of a subset of non-volatile storage elements.

3. An apparatus according to claim 1, wherein at least one of said one or more verification selection circuits comprises:

a sense circuit in communication with a first non-volatile storage element;

a programming mode indication circuit, in communication with said sense circuit, providing an output indicating whether said first non-volatile storage element is in a coarse programming mode or a fine programming mode based on said sense circuit; and

a selection circuit in communication with said programming mode indication circuit, said selection circuit applies a coarse verification signal to said first non-volatile storage element if said first non-volatile storage element is in said coarse programming mode and applies a fine verification signal to said first non-volatile storage element if said first non-volatile storage element is in said fine programming mode.

4. An apparatus according to claim 1, wherein at least one of said one or more verification selection circuits comprises:

a storage unit, said storage unit storing data indicating whether a first non-volatile storage element is in a coarse programming mode or a fine programming mode;

a first switch in communication with said first non-volatile storage element;

sense circuit connected to said first switch and providing an output to said storage unit, said storage unit uses said output from said sense circuit to indicate whether said first non-volatile storage element is in said coarse programming mode or said fine programming mode; and

a second switch in communication with said storage unit and having an output connected to said sense circuit, said second switch receiving a coarse reference signal and a fine reference signal and providing either said coarse reference signal or said fine reference signal at said output of said second switch in response to said storage unit.

5. An apparatus according to claim 4, wherein:

said non-volatile storage elements are flash memory devices.

6. An apparatus according to claim 4, wherein:

said coarse reference signal and said fine reference signal provide reference currents.

7. An apparatus according to claim 4, wherein:

said coarse reference signal and said fine reference signal provide reference voltages.

8. An apparatus according to claim 4, wherein:

said coarse reference signal and said fine reference signal provide an indication of discharge times.

9. An apparatus according to claim 1, wherein:

said coarse verification and said fine verification are performed using a discharge method.

10. An apparatus according to claim 1, wherein:

said programming circuit includes a controller and a state machine; and

said programming circuit is separate from said one or more verification selection circuits.

11. An apparatus according to claim 1, wherein:

said non-volatile storage elements are multi-state flash memory devices.

12. An apparatus according to claim 1, wherein:

said common control line is a word line.

13. A method for programming non-volatile storage elements, comprising:

providing a common programming signal to said non-volatile storage elements, said step of providing is part of a programming process that includes a coarse programming phase and a fine programming phase such that one or more of said non-volatile storage elements are in said coarse programming phase while one or more of said non-volatile storage elements are in said fine programming phase, said step of providing includes providing said common programming signal to a word line common to at least a subset of said one or more of said non-volatile storage elements that are in said coarse programming phase and said one or more of said non-volatile storage elements that are in said fine programming phase; and

performing coarse verification for said one or more of said non-volatile storage elements that are in said coarse programming phase while concurrently performing fine verification for said one or more of said non-volatile storage elements that are in said fine programming phase.

14. A method according to claim 13, wherein said step of performing comprises:

pre-charging a first bit line based on a coarse pre-charge signal if a first non-volatile storage element is in said coarse programming phase;

pre-charging said first bit line based on a fine pre-charge signal if said first non-volatile storage element is in said fine programming phase;

applying a verify signal to a control gate for said first non-volatile storage element; and

allowing said bit line to discharge for a fixed period of time.

15. A method according to claim 13, wherein said step of performing comprises:

pre-charging a first bit line for a first non-volatile storage element;

applying a verify signal to a control gate for said first non-volatile storage element;

determining a time for said bit line to discharge until a voltage or a current of said bit line reaches a predetermined value;

comparing a coarse compare value to said time, if said first non-volatile storage element is in said coarse programming phase; and

comparing a fine compare value to said time, if said first non-volatile storage element is in said fine programming phase.

16. A method according to claim 15, wherein:

said predetermined value is a first value if said first non-volatile storage element is in said coarse programming phase; and

said predetermined value is a second value if said first non-volatile storage element is in said fine programming phase.

17. A method according to claim 13, wherein:

said step of providing includes providing said common programming signal to steering gates.

18. A method for programming non-volatile storage elements, comprising:

providing a common programming signal to said non-volatile storage elements, said non-volatile storage elements are connected to a common control line, said step of providing is part of a programming process that includes a coarse programming phase and a fine programming phase such that one or more of said non-volatile storage elements are in said coarse programming phase while one or more of said non-volatile storage elements are in said fine programming phase; and

performing coarse verification for said one or more of said non-volatile storage elements that are in said coarse programming phase while concurrently performing fine verification for said one or more of said non-volatile storage elements that are in said fine programming phase.

19. An apparatus for programming non-volatile storage elements, comprising:

a programming circuit in communication with said non-volatile storage elements, said programming circuit programs said non-volatile storage elements together as part of a common coarse/fine programming process; and

one or more verification selection circuits in communication with said non-volatile storage elements, said one or more verification selection circuits cause a first subset of said non-volatile storage elements to be subjected to coarse verification concurrently while a second subset of said non-volatile storage elements are subjected to fine verification.

20. An apparatus for programming non-volatile storage elements, comprising:

an array of non-volatile storage elements;

a programming circuit in communication with said array of non-volatile storage elements, said programming circuit programs said array of non-volatile storage elements using a coarse/fine programming process; and

one or more verification selection circuits in communication with said array of non-volatile storage elements, said one or more verification selection circuits cause a first subset of said array of non-volatile storage elements to be subjected to coarse verification concurrently while a second subset of said array of non-volatile storage elements are subjected to fine verification.

21. A method for programming non-volatile storage elements, comprising:

providing a programming signal to a set of non-volatile storage elements being programmed together as part of a common coarse/fine programming process that includes a coarse programming phase and a fine programming phase such that one or more of said non-volatile storage elements are in said coarse programming phase while one or more of said non-volatile storage elements are in said fine programming phase; and

performing coarse verification for said one or more of said non-volatile storage elements that are in said coarse programming phase while concurrently performing fine verification for said one or more of said non-volatile storage elements that are in said fine programming phase.

22. A method according to claim 21, wherein:

said set of non-volatile storage elements are flash memory devices.

23. A method according to claim 21, wherein:

said set of non-volatile storage elements are multi-state flash memory devices.

24. A method according to claim 21, further comprising:

using said coarse verification to determine when a particular non-volatile storage element completes said coarse programming phase and cause said particular non-volatile storage element to begin said fine programming phase.

25. A method according to claim 24, wherein:

following said particular non-volatile storage element beginning said fine programming phase, said particular non-volatile storage element begins said fine verification.

26. A method according to claim 24, wherein:

causing said particular non-volatile storage element to begin said fine programming phase includes raising a bit line voltage.

27. A method according to claim 24, wherein said step of performing comprises:

performing said coarse verification for said particular non-volatile storage element without performing said fine verification for said particular non-volatile storage element, if said particular non-volatile storage element is determined to be in said coarse programming phase; and

performing said fine verification for said particular non-volatile storage element without performing said coarse verification for said particular non-volatile storage element, if said particular non-volatile storage element is determined to be in said fine programming phase.

28. A method according to claim 21, wherein:

said coarse verification and said fine verification are based on a bit line discharge process.

29. A method according to claim 21, wherein:

said set of non-volatile storage elements are connected to a common word line.