Hybrid architecture for realizing a random numbers generator
First Claim
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1. A hybrid architecture for realizing a random numbers generator, comprising:
- a digital circuitry portion, able to provide for a random bytes sequence; and
an analog circuitry portion coupled to the digital circuitry portion and able to provide a true random seed, wherein the analog circuitry portion includes an output bus connected to the digital circuitry portion and the digital circuitry portion comprises;
a plurality of linear feedback shift registers connected to the output bus of the analog circuitry portion; and
a clock generator comprising a plurality of clock oscillators structured to provide an irregular clock signal to the linear feedback shift registers.
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Abstract
A hybrid architecture for realizing a random numbers generator comprising a digital circuitry portion able to provide for a random bytes sequence as well as an analog circuitry portion able to provide a seed of the true random type is described.
62 Citations
19 Claims
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1. A hybrid architecture for realizing a random numbers generator, comprising:
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a digital circuitry portion, able to provide for a random bytes sequence; and an analog circuitry portion coupled to the digital circuitry portion and able to provide a true random seed, wherein the analog circuitry portion includes an output bus connected to the digital circuitry portion and the digital circuitry portion comprises; a plurality of linear feedback shift registers connected to the output bus of the analog circuitry portion; and a clock generator comprising a plurality of clock oscillators structured to provide an irregular clock signal to the linear feedback shift registers. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A random numbers generator comprising:
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a digital circuitry portion; an analog circuitry portion; and a bus connecting the analog circuitry portion to the digital circuitry portion, wherein the digital circuitry portion comprises; a clock generator in turn comprising a plurality of clock oscillators structured to output an irregular clock signal; and a plurality of linear feedback shift registers, each having a first input connected to an output of the clock generator and a second input connected to the bus. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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17. A method for generating a random number comprising the following phases:
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providing a first random sequence by means of an analog circuitry portion of a random numbers generator; and providing a random number by means of a digital circuitry portion of a random numbers generator using the first random sequence as a starting sequence, wherein said phase of providing a random number by means of the digital circuitry portion of the random numbers generator comprises a phase of changing of frequencies of a plurality of clock oscillators comprised in the digital circuitry portion in function of said first random sequence obtained by means of the analog circuitry portion of the random numbers generator. - View Dependent Claims (18, 19)
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Specification