Up-conversion of a down-converted baseband signal in a direct conversion architecture without the baseband signal passing through active elements

• US 7,139,546 B1
• Filed: 04/29/2003
• Issued: 11/21/2006
• Est. Priority Date: 04/29/2003
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: ON Semiconductor Corporation
• Inventors: Rice, Jeremy J., Petrov, Andrei R.
• Primary Examiner(s): Urban, Edward F.
• Assistant Examiner(s): CHOW, CHARLES CHIANG
• Application Number:
  US10/426,225
• Time in Patent Office: 1,302 Days
• Field of Search: 455/323, 455/425, 455/424, 455/561, 455/550.1, 455/575.1, 455/456.5, 455/456.6, 455/324, 455/326, 455/333, 455/334, 455/344, 455/67.13, 455/330, 455/278.1, 455/296, 455/189.1, 455/137, 455/130, 455/146, 455/209, 455/234.1, 455/250.1, 455/241.1, 455/239.1, 455/254.1, 455/304, 455/255, 455/256, 455/196.1, 455/264, 455/313, 455/207, 327/209, 327/210, 327/203, 327/116, 327/207, 327/113, 327355-359, 333/172, 333/184, 333/168, 333/174, 333/181, 333/185
• US Class Current: 455/323
• CPC Class Codes: H04B 1/30 for homodyne or synchrodyne receivers demodulator circuits H03D1/22

Abstract

A direct conversion circuit that not only down-converts the received modulated signal using a down-converting mixer into a baseband signal, but also, after performing a passive low pass filtering to remove higher-order components, performs up-conversion of the baseband signal using an up-converting mixer. Active elements such as highly sensitive amplifiers do not operate on the baseband signal itself, but on the up-converted version of that baseband signal, thereby reducing the 1/f noise introduced by those active elements. The downstream circuitry after the up-conversion may be coupled by intervening capacitors since the downstream circuitry is operating on a higher frequency signal. Accordingly, the DC offset introduced by the downstream active elements is reduced.

Claims

1. A direct conversion receiver circuit comprising the following:

a down-converting mixer that is configured to down-convert a received modulated signal to thereby generate a baseband signal;

a low pass filter comprising a resister-capacitor circuit having at least one pole that is coupled to the down-converting mixer so as to filter high frequency components of the down-converted signal to thereby generate a filtered down-converted signal;

an up-converting mixer that is coupled to the low pass filter so as to receive and up-convert the filtered down-converted signal, wherein there are no active components that operate on the down-converted baseband signal prior to being up-converted;

an amplifier configured to receive and amplify the up-converted signal; and

an up-converting local oscillator that is configured to generate a first up-conversion control signal and a second up-conversion control signal that represents a binary complement of the first up-conversion control signal, wherein the up-converting mixer comprises the following;

a first and second input terminal and first and second output terminals;

a first field-effect transistor having a source or drain terminal coupled to a first output terminal of the down-converting mixer so as to receive at least a filtered version of the signal provided on the first output terminal of the down-converting mixer, the other of the source or drain terminal of the first field-effect transistor coupled to the first output terminal of the up-converting mixer, a gate terminal of the first field-effect transistor configured to receive the second up-converting control signal;

a second field-effect transistor having a source or drain terminal coupled to the first output terminal of the down-converting mixer so as to receive at least a filtered version of the signal provided on the first output terminal of the down-converting mixer, the other of the source or drain terminal of the second field-effect transistor coupled to the second output terminal of the up-converting mixer, a gate terminal of the second field-effect transistor configured to receive the first up-converting control signal;

a third field-effect transistor having a source or drain terminal coupled to a second output terminal of the down-converting mixer so as to receive at least a filtered version of the signal provided on the second output terminal of the down-converting mixer, the other of the source or drain terminal of the third field-effect transistor coupled to the first output terminal of the up-converting mixer, a gate terminal of the third field-effect transistor configured to receive the first up-converting control signal; and

a fourth field-effect transistor having a source or drain terminal coupled to the second output terminal of the down-converting mixer so as to receive at least a filtered version of the signal provided on the second output terminal of the down-converting mixer, the other of the source or drain terminal of the fourth field-effect transistor coupled to the second output terminal of the up-converting mixer, a gate terminal of the fourth field-effect transistor configured to receive the second up-converting control signal.

2. A direct conversion receiver circuit in accordance with claim 1, wherein the first output terminal of the up-converting mixer is capacitively coupled to a first input terminal of the amplifier, the second output terminal of the up-converting mixer being capacitively coupled to a second input terminal of the amplifier.

3. A receiver circuit in accordance with claim 2, wherein a first output terminal of the amplifier is capacitively coupled to a first input terminal of a first band pass filter.

4. A direct conversion receiver circuit comprising the following:

an in-phase down-converting mixer that is configured to down-convert a received modulated signal to thereby generate an in-phase portion of a baseband signal;

an in-phase low pass filter that is coupled to the in-phase down-converting mixer so as to filter high frequency components of the down-converted signal to thereby generate a filtered in-phase down-converted signal;

an in-phase up-converting mixer that is coupled to the in-phase low pass filter so as to receive and up-convert the in-phase filtered down-converted signal, wherein there are no active components that operate on the in-phase down-converted baseband signal prior to being up-converted;

an in-phase amplifier configured to receive and amplify the up-converted signal;

a quadrature-phase down-converting mixer that is configured to down-convert the received modulated signal to thereby generate a quadrature-phase portion of the baseband signal;

a quadrature-phase low pass filter that is coupled to the quadrature-phase down-converting mixer so as to filter high frequency components of the down-converted signal to thereby generate a filtered quadrature-phase down-converted signal;

a quadrature-phase up-converting mixer that is coupled to the quadrature-phase low pass filter so as to receive and up-convert the filtered quadrature-phase down-converted signal, wherein there are no active components that operate on the quadrature-phase down-converted baseband signal prior to being up-converted;

a quadrature-phase amplifier configured to receive and amplify the up-converted signal; and

a down-converting local oscillator that is configured to generate a first down-conversion control signal a second down-conversion control signal that is approximately 180 degrees out of phase with the first down-conversion control signal, a third down-conversion control signal that represents a binary complement of the first down-conversion control signal, and a fourth down-conversion control signal that represents a binary complement of the second down-conversion control signal, wherein the in-phase down-converting mixer comprises;

an input terminal and first and second output terminals;

first, second, and third field-effect transistors coupled in series between the input terminal of the in-phase down-converting mixer and the first output terminal of the in-phase down-converting mixer, the first, second and third field-effect transistors coupled to the down-converting local oscillator such that the first down-converting control signal is applied to a gate terminal of the second field-effect transistor, and such that the third down-converting control signal is applied to a gate terminal of the first and third field-effect transistors; and

fourth, fifth, and sixth field-effect transistors coupled in series between the input terminal of the in-phase down-converting mixer and the second output terminal of the in-phase down-converting mixer, the fourth, fifth, and sixth field-effect transistors coupled to the down-converting local oscillator such that the second down-converting control signal is applied to a gate terminal of the fifth field-effect transistor, and such that the fourth down-converting control signal is applied to a gate terminal of the fourth and sixth field-effect transistors.

5. A direct conversion receiver circuit in accordance with claim 4, further comprising an up-converting local oscillator that is configured to generate a first up-conversion control signal and a second up-conversion control signal that represents a binary complement of the first up-conversion control signal, wherein the in-phase up-converting mixer comprises the following:

a first and second input terminal and first and second output terminals;

a seventh field-effect transistor having a source or drain terminal coupled to the first output terminal of the in-phase down-converting mixer so as to receive at least a filtered version of the signal provided on the first output terminal of the in-phase down-converting mixer, the other of the source or drain terminal of the seventh field-effect transistor coupled to the first output terminal of the in-phase up-converting mixer, a gate terminal of the seventh field-effect transistor configured to receive the second up-converting control signal;

an eighth field-effect transistor having a source or drain terminal coupled to the first output terminal of the in-phase down-converting mixer so as to receive at least a filtered version of the signal provided on the first output terminal of the in-phase down-converting mixer, the other of the source or drain terminal of the eighth field-effect transistor coupled to the second output terminal of the in-phase up-converting mixer, a gate terminal of the eighth field-effect transistor configured to receive the first up-converting control signal;

a ninth field-effect transistor having a source or drain terminal coupled to the second output terminal of the in-phase down-converting mixer so as to receive at least a filtered version of the signal provided on the second output terminal of the in-phase down-converting mixer, the other of the source or drain terminal of the ninth field-effect transistor coupled to the first output terminal of the in-phase up-converting mixer, a gate terminal of the ninth field-effect transistor configured to receive the first up-converting control signal;

a tenth field-effect transistor having a source or drain terminal coupled to the second output terminal of the in-phase down-converting mixer so as to receive at least a filtered version of the signal provided on the second output terminal of the in-phase down-converting mixer, the other of the source or drain terminal of the tenth field-effect transistor coupled to the second output terminal of the in-phase up-converting mixer, a gate terminal of the tenth field-effect transistor configured to receive the second up-converting control signal.

6. A direct conversion receiver circuit comprising the following:

a down-converting mixer that is configured to down-convert a received modulated signal to thereby generate a baseband signal;

a low pass filter that is coupled to the down-converting mixer so as to filter high frequency components of the down-converted signal to thereby generate a filtered down-converted signal;

an up-converting mixer that is coupled to the low pass filter so as to receive and up-convert the filtered down-converted signal, wherein there are no active components that operate on the down-converted baseband signal prior to being up-converted;

an amplifier configured to receive and amplify the up-converted signal; and

an up-converting local oscillator that is configured to generate a first up-conversion control signal and a second up-conversion control signal that represents a binary complement of the first up-conversion control signal, wherein the up-converting mixer comprises the following;

a first and second input terminal and first and second output terminals;

a first nMOSFET having a source or drain terminal coupled to a first output terminal of the down-converting mixer so as to receive at least a filtered version of the signal provided on the first output terminal of the down-converting mixer, the other of the source or drain terminal of the first field-effect transistor coupled to the first output terminal of the up-converting mixer, a gate terminal of the first field-effect transistor configured to receive the second up-converting control signal;

a second nMOSFET having a source or drain terminal coupled to the first output terminal of the down-converting mixer so as to receive at least a filtered version of the signal provided on the first output terminal of the down-converting mixer, the other of the source or drain terminal of the second field-effect transistor coupled to the second output terminal of the up-converting mixer a gate terminal of the second field-effect transistor configured to receive the first up-converting control signal;

a third nMOSFET having a source or drain terminal coupled to a second output terminal of the down-converting mixer so as to receive at least a filtered version of the signal provided on the second output terminal of the down-converting mixer, the other of the source or drain terminal of the third field-effect transistor coupled to the first output terminal of the up-converting mixer, a gate terminal of the third field-effect transistor configured to receive the first up-converting control signal;

a fourth nMOSFET having a source or drain terminal coupled to the second output terminal of the down-converting mixer so as to receive at least a filtered version of the signal provided on the second output terminal of the down-converting mixer, the other of the source or drain terminal of the fourth field-effect transistor coupled to the second output terminal of the up-converting mixer a gate terminal of the fourth field-effect transistor configured to receive the second up-converting control signal;

a first p-type field-effect transistor having a source or drain terminal coupled to the first output terminal of the down-converting mixer so as to receive at least a filtered version of the signal provided on the first output terminal of the down-converting mixer, the other of the source or drain terminal of the first p-type field-effect transistor coupled to the first output terminal of the up-converting mixer, a gate terminal of the first p-type field-effect transistor configured to receive the first up-converting control signal;

a second p-type field-effect transistor having a source or drain terminal coupled to the first output terminal of the down-converting mixer so as to receive at least a filtered version of the signal provided on the first output terminal of the down-converting mixer, the other of the source or drain terminal of the second p-type field-effect transistor coupled to the second output terminal of the up-converting mixer a gate terminal of the second p-type field-effect transistor configured to receive the second up-converting control signal;

a third p-type field-effect transistor having a source or drain terminal coupled to the second output terminal of the down-converting mixer so as to receive at least a filtered version of the signal provided on the second output terminal of the down-converting mixer, the other of the source or drain terminal of the third p-type field-effect transistor coupled to the first output terminal of the up-converting mixer a gate terminal of the third p-type field-effect transistor configured to receive the second up-converting control signal; and

a fourth p-type field-effect transistor having a source or drain terminal coupled to the second output terminal of the down-converting mixer so as to receive at least a filtered version of the signal provided on the second output terminal of the down-converting mixer, the other of the source or drain terminal of the fourth p-type field-effect transistor coupled to the second output terminal of the up-converting mixer, a gate terminal of the fourth p-type field-effect transistor configured to receive the first up-converting control signal.

7. A direct conversion receiver circuit comprising the following:

a down-converting mixer that is configured to down-convert a received modulated signal to thereby generate a baseband signal;

a low pass filter comprising a resister-capacitor circuit having four poles that is coupled to the down-converting mixer so as to filter high frequency components of the down-converted signal to thereby generate a filtered down-converted signal;

an up-converting mixer that is coupled to the low pass filter so as to receive and up-convert the filtered down-converted signal wherein there are no active components that operate on the down-converted baseband signal prior to being up-converted;

an amplifier configured to receive and amplify the up-converted signal; and

an up-converting local oscillator that is configured to generate a first up-conversion control signal and a second up-conversion control signal that represents a binary complement of the first up-conversion control signal, wherein the up-converting mixer comprises the following;

a first and second input terminal and first and second output terminals;

a first field-effect transistor having a source or drain terminal coupled to a first output terminal of the down-converting mixer so as to receive at least a filtered version of the signal provided on the first output terminal of the down-converting mixer, the other of the source or drain terminal of the first field-effect transistor coupled to the first output terminal of the up-converting mixer, a gate terminal of the first field-effect transistor configured to receive the second up-converting control signal;

a second field-effect transistor having a source or drain terminal coupled to the first output terminal of the down-converting mixer so as to receive at least a filtered version of the signal provided on the first output terminal of the down-converting mixer, the other of the source or drain terminal of the second field-effect transistor coupled to the second output terminal of the up-converting mixer, a gate terminal of the second field-effect transistor configured to receive the first up-converting control signal;

a third field-effect transistor having a source or drain terminal coupled to a second output terminal of the down-converting mixer so as to receive at least a filtered version of the signal provided on the second output terminal of the down-converting mixer, the other of the source or drain terminal of the third field-effect transistor coupled to the first output terminal of the up-converting mixer, a gate terminal of the third field-effect transistor configured to receive the first up-converting control signal; and

a fourth field-effect transistor having a source or drain terminal coupled to the second output terminal of the down-converting mixer so as to receive at least a filtered version of the signal provided on the second output terminal of the down-converting mixer, the other of the source or drain terminal of the fourth field-effect transistor coupled to the second output terminal of the up-converting mixer a gate terminal of the fourth field-effect transistor configured to receive the second up-converting control signal.