One-way transaction tagging in a switch crossbar

• US 7,139,836 B1
• Filed: 08/08/2001
• Issued: 11/21/2006
• Est. Priority Date: 08/08/2001
• Status: Active Grant

• Current Assignee: Zarbana Digital Fund LLC (Intellectual Ventures LLC)
• Original Assignee: Pasternak Solutions LLC (Intellectual Ventures LLC)
• Inventors: Purcell, Stephen Clark, Kimura, Scott
• Primary Examiner(s): Najjar, Saleh
• Assistant Examiner(s): Hamza, Faruk
• Application Number:
  US09/925,160
• Time in Patent Office: 1,931 Days
• Field of Search: 709/203, 709211-216, 709/218, 709/236, 709/245, 709/246, 709/238, 370352-357, 370/392, 370/428
• US Class Current: 709/238
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence

Abstract

A method and computer program product includes, at a sender, identifying a forward item including a transmit portion and a retain portion, generating a tag, associating the tag with the retain portion, sending the transmit portion, but not the tag, to a target; at the target, receiving the transmit portion, identifying a return portion corresponding to the transmit portion, independently generating the tag, associating the tag with the return portion, sending the return portion and the tag to the sender; and at the sender, receiving the return portion and the tag, identifying the retain portion using the tag, and associating the return portion with the retain portion to create a reverse item.

Claims

1. An apparatus comprising:

a sender including

a first controller configured to receive a data item including a transmit data portion and a retain data portion;

a first tag generator configured to generate a first tag and associate the first tag with the retain data portion;

a first transmitter configured to send the transmit data portion, but not the first tag, to a target;

wherein the target includes

a first receiver configured to receive the transmit data portion sent by the sender;

a second controller configured to identify return data corresponding to the transmit data portion;

a second tag generator configured to independently generate a second tag and associate the second tag with the return data;

a second transmitter configured to send the return data and the second tag to the sender;

wherein the sender includes

a second receiver configured to receive the return data and the second tag; and

wherein the first controller is configured to identify the retain data portion using the second tag and associate the return data with the retain data portion to create a reverse item.

2. The apparatus of claim 1, further comprising:

means for initializing the first and second tag generators to generate identical tags in identical order.

3. The apparatus of claim 2, wherein each of the first and second tag generators includes a buffer and means for initializing comprises:

means for loading each buffer with a set of tags such that both buffers contain identical tags in identical order and no tag in the set is the same as any other tag in the set.

4. The apparatus of claim 3, wherein the first tag generator is configured to remove first the tag from the buffer.

5. The apparatus of claim 4, wherein the first controller is configured to return the first tag to the first tag generator after associating the return data with the retain data portion.

6. The apparatus of claim 5, wherein the second controller is configured to return the second tag to the second tag generator after sending the return data.

7. The apparatus of claim 1, wherein the sender and target are different layers of a multi-layer switch coupling a processor to a memory, the forward item includes a memory transaction, and the reverse item includes a result of the memory transaction.

8. The apparatus of claim 7, wherein the processor is a graphics processor.

9. The apparatus of claim 1, wherein the sender is a processor and the target is a layer in a multiple-layer switch having a plurality of layers.

10. The apparatus of claim 9, wherein the processor is a graphics processor.

11. The apparatus of claim 2, wherein each of the first and second tag generators includes a counter and means for initializing comprises:

means for setting both counters to the same value.

12. The apparatus of claim 11, wherein means for associating a tag comprises:

means for incrementing the counter; and

means for associating the value output by the counter with the tag.

13. The apparatus of claim 11, wherein the counters are incremented continuously according to a clock signal and each tag generator is configured to associate the value output by the counter with the tag.

14. A method comprising:

at a sender,

receiving a data item including a transmit data portion and a retain data portion;

generating a tag;

associating the tag with the retain data portion;

sending the transmit data portion, but not the tag, to a target;

at the target,

receiving the transmit data portion;

identifying return data corresponding to the transmit data portion;

independently generating a second tag;

associating the second tag with the return data;

sending the return data and the second tag to the sender;

at the sender;

receiving the return data and the second tag;

identifying the retain data portion using the second tag; and

associating the return data with the retain data portion to create a reverse item.

15. The method of claim 14, further comprising:

initializing the first and second tag generators to generate the identical tags in identical order.

16. The method of claim 15, wherein each of the first and second tag generators is a buffer and the initializing comprises:

loading each buffer with a set of tags such that both buffers contain identical tags in identical order and no tag in the set is the same as any other tag in the set.

17. The method of claim 16, wherein associating a tag comprises:

removing the tag from the buffer.

18. The method of claim 17, further comprising:

returning the tag to the first tag generator after associating the return data with the retain data portion.

19. The method of claim 18, further comprising:

returning the second tag to the second tag generator after sending the return data.

20. The method of claim 14, wherein the sender and target are different layers of a multi-layer switch coupling a processor to a memory, the forward item includes a memory transaction, and the reverse item includes a result of the memory transaction.

21. The method of claim 20, wherein the processor is a graphics processor.

22. The method of claim 14, wherein the sender is a processor and the target is a layer in a multiple-layer switch having a plurality of layers.

23. The method of claim 22, wherein the processor is a graphics processor.

24. The method of claim 15, wherein each of the first and second tag generators is a counter and initializing comprises:

setting both counters to the same value.

25. The method of claim 24, wherein associating a tag comprises:

incrementing the counter; and

associating the value output by the counter with the tag.

26. The method of claim 24, wherein the counters are incremented continuously according to a clock signal and associating a tag comprises:

associating the value output by the counter with the tag.

27. A computer program product, tangibly stored on a computer-readable medium, comprising instructions operable to cause a programmable processor to:

at a sender,

receive a data item including a transmit data portion and a retain data portion;

generate a tag;

associate the tag with the retain data portion;

send the transmit data portion, but not the tag, to a target;

at the target,

receive the transmit data portion;

identify return corresponding to the transmit data portion;

independently generate a second tag;

associate the second tag with the return data portion;

send the return and the second tag to the sender;

at the sender;

receive the return data and the second tag;

identify the retain data portion using the second tag; and

associate the return data with the retain data portion to create a reverse item.

28. The computer program product of claim 27, further comprising instructions operable to cause a programmable processor to:

initialize the first and second tag generators to generate identical tags in identical order.

29. The computer program product of claim 28, wherein each of the first and second tag generators is a buffer and instructions operable to cause a programmable processor to initialize comprise instructions operable to cause a programmable processor to:

load each buffer with a set of tags such that both buffers contain identical tags in identical order and no tag in the set is the same as any other tag in the set.

30. The computer program product of claim 29, wherein instructions operable to cause a programmable processor to associate a tag comprise instructions operable to cause a programmable processor to:

remove the tag from the buffer.

31. The computer program product of claim 30, further comprising instructions operable to cause a programmable processor to:

return the tag to the first tag generator after associate the return data with the retain data portion.

32. The computer program product of claim 31, further comprising instructions operable to cause a programmable processor to:

return the second tag to the second tag generator after send the return data.

33. The computer program product of claim 27, wherein the sender and target are different layers of a multi-layer switch coupling a processor to a memory, the forward item includes a memory transaction, and the reverse item includes a result of the memory transaction.

34. The computer program product of claim 33, wherein the processor is a graphics processor.

35. The computer program product of claim 27, wherein the sender is a processor and the target is a layer in a multiple-layer switch having a plurality of layers.

36. The computer program product of claim 35, wherein the processor is a graphics processor.

37. The computer program product of claim 28, wherein each of the first and second tag generators is a counter and instructions operable to cause a programmable processor to initialize comprise instructions operable to cause a programmable processor to:

set both counters to the same value.

38. The computer program product of claim 37, wherein instructions operable to cause a programmable processor to associate a tag comprise instructions operable to cause a programmable processor to:

increment the counter; and

associate the value output by the counter with the tag.

39. The computer program product of claim 37, wherein the counters are incremented continuously according to a clock signal and instructions operable to cause a programmable processor to associate a tag comprise instructions operable to cause a programmable processor to:

associate the value output by the counter with the tag.