Memory protection system and method for computer architecture for broadband networks

• US 7,139,882 B2
• Filed: 02/21/2003
• Issued: 11/21/2006
• Est. Priority Date: 03/22/2001
• Status: Expired due to Term

• Current Assignee: Sony Computer Entertainment Incorporated (Sony Group Corp.)
• Original Assignee: Sony Computer Entertainment Incorporated (Sony Group Corp.)
• Inventors: Yamazaki, Takeshi, Suzuoki, Masakazu
• Primary Examiner(s): Nguyen, Hiep T.
• Application Number:
  US10/371,322
• Publication Number:
  US 20030229765A1
• Time in Patent Office: 1,369 Days
• Field of Search: 711/147, 711/153, 711/148, 711/173
• US Class Current: 711/153
• CPC Class Codes: G06F 12/1466 Key-lock mechanism
• CPC Class Codes: H04L 69/12 Protocol engines

Abstract

A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network. A system and method for creating a dedicated pipeline for processing streaming data also are provided.

Claims

1. A computer processing system, said processing system comprising:

a plurality of first processing units;

a main memory shared by said plurality of first processing units; and

a second processing unit for controlling said plurality of first processing units, said second processing unit being operable to dynamically assign portions of said main memory among said plurality of first processing units.

2. The computer processing system of claim 1, further comprising means for preventing certain of said plurality of first processing units from accessing said portions of main memory assigned to other ones of said plurality of first processing units.

3. The computer processing system of claim 1, further comprising a memory access controller for preventing certain of said plurality of first processing units from accessing said portions of main memory assigned to other ones of said plurality of first processing units.

4. The computer processing system of claim 1, wherein the dynamic assignment to at least one of said plurality of first processing units is based on a request to said second processing unit.

5. The computer processing system of claim 4, wherein the request comes from a software cell.

6. The computer processing system of claim 4, wherein the request includes an amount of space required from said main memory to be assigned.

7. A computer processing method, said method comprising:

controlling a plurality of first processing units with a second processing unit; and

dynamically assigning with said second processing unit portions of a main memory among said plurality of first processing units such that said main memory is shared among said plurality of first processing units.

8. The computer processing method of claim 7, wherein the dynamically assigning step includes the step of assigning one of said plurality of first processing units to a portion of said main memory such that the remainder of said plurality of first processing units are locked out of accessing said portion.

9. The computer processing method of claim 7, wherein the dynamically assigning step includes the step of receiving a request for assigning a portion of said memory to at least one of said plurality of first processing units.

10. The computer processing method of claim 9, wherein the request comes from a software cell.

11. The computer processing method of claim 9, wherein the request includes an amount of space required from said main memory to be assigned.