Methods and arrangements to interface memory

• US 7,139,890 B2
• Filed: 04/30/2002
• Issued: 11/21/2006
• Est. Priority Date: 04/30/2002
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Hall, Clifford D., Piazza, Thomas A., Jensen, Richard W., Moran, Douglas R.
• Primary Examiner(s): CHACE, CHRISTIAN
• Application Number:
  US10/135,149
• Publication Number:
  US 20030204693A1
• Time in Patent Office: 1,666 Days
• Field of Search: 707/8, 707/9, 709/215, 709/226, 710/28, 710/38, 710/200, 711/149, 711/151, 711/152, 711/153, 711/163, 711/173, 713/162, 713/164, 713/169, 713/182, 713/193, 713/201
• US Class Current: 711/163
• CPC Class Codes: G06F 12/1483 using an access-table, e.g. matrix or list

Abstract

Methods and arrangements to interface memory are described. Many embodiments comprise comparing a transaction or access from a source to memory addresses associated with the source to determine whether an address associated with the transaction is accessible by the source. Some embodiments may comprise defining protected memory. Several embodiments may comprise defining protected memory by, for example, determining a configuration for memory. Such embodiments may comprise protecting a memory location or limiting access to memory addresses associated with a protected memory location. Some of these embodiments may comprise accessing registers to define protected memory and verifying accesses to a memory location according to the definition of protected memory. Further embodiments may comprise generating an association between a source of an access and a memory location and storing the association to facilitate access to the memory location by the source.

Claims

1. A method, comprising:

receiving by a hub a transaction from a port;

comparing an address associated with the transaction to a memory location associated with the port; and

determining by the hub whether the port has access to the address without requesting verification by a processor based upon said comparing of said memory location by determining whether the transaction is associated with a protected memory location, and if so, determining that the transaction is permitted in accordance with a definition of protected memory being an association of memory locations with addresses in memory.

2. The method of claim 1, further comprising blocking the transaction based upon a determination that the address is associated with protected memory that is inaccessible by the port.

3. The method of claim 2, wherein blocking the transaction comprises resetting part of a platform.

4. The method of claim 2, wherein blocking the transaction comprises responding to the transaction with a pattern of bits.

5. The method of claim 1, wherein said comparing comprises comparing the address to a graphics table, wherein the graphics table indicates addresses accessible by the port.

6. The method of claim 1, wherein said determining comprises determining that the address is associated with an unprotected memory location to verify that the address is accessible by the port.

7. The method of claim 1, wherein the transaction is a request from a thread operating on a processor.

8. The method of claim 1, wherein the hub is coupled to the processor and the memory.

9. The method of claim 8, wherein the hub is further coupled to a graphics device.

10. The method of claim 9, wherein the hub is further coupled to an input/output device.

11. An apparatus communicatively coupled to both a processor and an input/output (I/O device), comprising:

a port to receive an access including an alias for a memory address, said port being one of a plurality of ports being coupled to one of the processor and the I/O device;

comparison circuitry coupled with said port to translate the alias based upon an entry in an address translation table and to compare the translate address with address accessible by said port; and

approval circuitry to determine whether to block the transaction based upon the address in response to said comparison circuitry.

12. The apparatus of claim 11, wherein said comparison circuitry comprises circuitry to determine whether the address is associated with an unprotected memory location.

13. The apparatus of claim 11, wherein said approval circuitry comprises circuitry to approve the transaction based upon a determination that the address is accessible by said port.

14. The apparatus of claim 11, wherein the access is a request from a thread operating on the processor.