Extended instruction set for packet processing applications

• US 7,139,901 B2
• Filed: 09/07/2001
• Issued: 11/21/2006
• Est. Priority Date: 02/08/2000
• Status: Expired due to Term

• Current Assignee: ARM Finance Overseas Limited (SoftBank Group Corp.)
• Original Assignee: MIPS Technologies Incorporated (Wave Computing, Inc.)
• Inventors: Musoll, Enrique, Nemirovsky, Mario, Melvin, Stephen
• Primary Examiner(s): Nguyen, Hanh
• Application Number:
  US09/948,919
• Publication Number:
  US 20020054603A1
• Time in Patent Office: 1,901 Days
• Field of Search: 712/10, 712/14, 712/21, 712/23, 712/22, 712/201, 712/203, 712/205, 712/206, 712/207, 712/215, 712/228, 712/200, 712/221, 712/227, 709/213, 709/229, 709/214, 709/226, 370/410, 370/412, 370/413, 370/415, 711/2
• US Class Current: 712/228
• CPC Class Codes: G06F 9/30003 Arrangements for executing specific machine instructions
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/5016 the resource being the memory
• CPC Class Codes: G06F 9/546 Message passing systems or structures, e.g. queues
• CPC Class Codes: H04L 47/2441 relying on flow classification, e.g. using integrated services [IntServ]
• CPC Class Codes: H04L 47/32 by discarding or delaying data units, e.g. packets or frames
• CPC Class Codes: H04L 47/621 Individual queue per connection or flow, e.g. per VC
• CPC Class Codes: H04L 47/6215 Individual queue per QOS, rate or priority
• CPC Class Codes: H04L 49/201 Multicast operation; Broadcast operation
• CPC Class Codes: H04L 49/205 Quality of Service based
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9073 Early interruption upon arrival of a fraction of a packet

Abstract

A software program extension for a dynamic multi-streaming processor is disclosed. The extension comprising an instruction set enabling coordinated interaction between a packet management component and a core processing component of the processor. The software program comprises, a portion thereof for managing packet uploads and downloads into and out of memory, a portion thereof for managing specific memory allocations and de-allocations associated with enqueueing and dequeuing data packets, a portion thereof for managing the use of multiple contexts dedicated to the processing of a single data packet; and a portion thereof for managing selection and utilization of arithmetic and other context memory functions associated with data packet processing. The extension complements standard data packet processing program architecture for specific use for processors having a packet management unit that functions independently from a streaming processor unit.

Claims

1. A software program extension for a dynamic multi-streaming processor, the software program extension stored in a computer readable medium comprising an instruction set enabling coordinated interaction between a packet management component and a stream processing component of the processor comprising:

a portion thereof for managing packet uploads and downloads into and out of memory;

a portion thereof for managing specific memory allocations and de-allocations associated with enqueueing and dequeuing data packets;

a portion thereof for managing the use of multiple contexts dedicated to the processing of a single data packet; and

a portion thereof for managing selection and utilization of one or more arithmetic functions and other context memory functions associated with data packet processing;

characterized in that the software program extension complements standard data packet processing program architecture for specific use for processors having a packet management unit that functions independently from a stream processor unit.

2. The software program extension of claim 1 wherein the dynamic multi-streaming processor functions as a data router coupled to a data packet network.

3. The software program extension of claim 2 wherein the data packet network is the Internet network.

4. The software program extension of claim 1 wherein the coordinated interaction includes conununication of requests, commands, and notifications that do not require responses.

5. The software program extension of claim 1 wherein the portion for managing packet uploads and downloads includes instructions for packet activation, packet completion, packet removal, packet identification, packet relocation, and packet update.

6. The software program extension of claim 5 wherein the packet removal and packet relocation instructions are associated with removal of a packet from memory and relocating a packet from one portion of memory to another.

7. The software program extension of claim 1 wherein the portion for managing memory allocations and de-allocations includes instructions for obtaining space in memory and for clearing previously allocated space in memory.

8. The software program extension of claim 7 wherein the memory is hardware controlled by a packet management component.

9. The software program extension of claim 1 wherein the software program extension is supported by a MIPS compatible processor architecture.

10. The software program extension of claim 1 wherein the portion for managing the use of multiple contexts includes instructions for obtaining an idle context, releasing an activated context, and for forcing nonuse of a context for predefined period of time.

11. The software program extension of claim 1 wherein the portion for managing selection and utilization of arithmetic and other context memory functions includes instructions for gathering information from memory for loading into a context, distributing information from a context into memory, selecting and accessing at least one addition function, and for selecting and accessing at least one subtraction function.

12. A software program extension for a dynamic multi-streaming processor, the software program extesion stored in a computer readable medium comprising an instruction set enabling coordinated interaction between a packet management component and a stream processing component of the processor comprising:

a portion thereof for managing packet uploads and downloads into and out of memory;

a portion thereof for managing specific memory allocations and de-allocations associated with enqueueing and dequeuing data packets;

a portion thereof for managing the use of multiple contexts dedicated to the processing of a single data packet, wherein the portion for managing the use of multiple contexts includes an instruction for forcing nonuse of a context for predefined period of time; and

a portion thereof for managing selection and utilization of one or more arithmetic functions and other context memory functions associated with data packet processing;

characterized in that the software provam extension complements standard data packet processing program architecture for specific use for processors having a packet management unit that functions independently from a stream processor unit.