Low power clocking systems and methods

• US 7,139,921 B2
• Filed: 06/14/2004
• Issued: 11/21/2006
• Est. Priority Date: 03/21/2001
• Status: Expired due to Term

• Current Assignee: SK Hynix Inc.
• Original Assignee: Gallitzin Allegheny LLC (Intellectual Ventures LLC)
• Inventors: Sherburne, Robert Warren Jr.
• Primary Examiner(s): Cao, Chun
• Application Number:
  US10/867,901
• Publication Number:
  US 20040243866A1
• Time in Patent Office: 890 Days
• Field of Search: 713/300, 713/320, 713/322, 713/323, 713/500, 713/501, 713/601
• US Class Current: 713/322
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 9/30083 Power or thermal control instructions
• CPC Class Codes: G06F 9/30094 Condition code generation, e.g. Carry, Zero flag
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/3869 Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A low power reconfigurable processor core includes one or more processing units, each unit having a clock input that controls the performance of the unit; and a controller having a plurality of clock outputs each coupled to a respective clock input of one of the processing units, the controller varying the clock frequency of each processing unit to optimize power consumption and processing power for a task.

Claims

1. An integrated circuit comprising:

a digital portion including;

a plurality of processors configured to execute one or more algorithms, each of the plurality of processors having a respective clock input to control a rate of processor performance; and

a controller having a plurality of clock outputs coupled to the respective clock input of the plurality of processors, wherein the controller is configured to vary a clock frequency of at least one of the plurality of processors to control the rate of processor performance; and

an analog portion coupled to the digital portion, the analog portion including at least one radio frequency (RF) transceiver.

2. The integrated circuit of claim 1, wherein the controller is configured to change one or more of the respective clock inputs on-the-fly.

3. The integrated circuit of claim 1, further comprising a buffer coupled between an output of a first one of the plurality of processors and an input of a second one of the plurality of processors, wherein the buffer is to be controlled by the same clock frequency as the first processor and at a different frequency than the second processor.

4. The integrated circuit of claim 1, wherein the controller is to vary the clock frequency of a subset of the plurality of processors as an ensemble.

5. The integrated circuit of claim 1, wherein the controller is to apply a different frequency clock to the respective clock input of at least some of the plurality of processors.

6. The integrated circuit of claim 1, wherein the controller is to provide the respective clock input of a first one of the plurality of processors with a first clock frequency for a first task and a second frequency for a second task.

7. The integrated circuit of claim 1, wherein the controller is to receive a master clock and to generate the plurality of clock outputs at a frequency of the master clock or a fraction thereof.

8. A method comprising:

wirelessly communicating via a first wireless protocol using a wireless device having a digital portion including a plurality of processors configured to execute one or more algorithms, each of the plurality of processors having a respective clock input, and a controller having a plurality of clock outputs coupled to the respective clock input of the plurality of processors, wherein the controller is configured to provide different clock frequencies to at least two of the plurality of processors, the wireless device including an analog portion coupled to the digital portion, the analog portion including at least one radio frequency (RF) transceiver; and

wirelessly communicating via a second wireless protocol using the wireless device.

9. The method of claim 8, wherein the first wireless protocol comprises a short-range wireless protocol and the second wireless protocol comprises a cellular radio protocol.

10. The method of claim 8, further comprising wirelessly communicating via the first wireless protocol and the second wireless protocol simultaneously via the wireless device.

11. The method of claim 8, further comprising wirelessly communicating by switching between the first wireless protocol and the second wireless protocol.

12. The method of claim 8, further comprising powering down a first one of the plurality of processors using the controller when the wireless device is not wirelessly communicating via the first wireless protocol.

13. A system comprising:

a first processor configured to execute application programs;

a wireless communicator coupled to the first processor, the wireless communicator including a digital portion having a plurality of processors, wherein at least a first and second of the plurality of processors are coupled in parallel to form a parallel processor path, wherein each of the plurality of processors includes a respective clock input, and a controller having a plurality of clock outputs coupled to the respective clock input of the plurality of processors, wherein the controller is configured to provide a first clock frequency to at least a first one of the plurality of processors and a second clock frequency to at least a second one of the plurality of processors, the wireless communicator further including an analog portion coupled to the digital portion, the analog portion including at least one radio frequency (RF) transceiver; and

an antenna coupled to the wireless communicator and configured to transmit and receive information via multiple wireless protocols.

14. The system of claim 13, further comprising a digitizer coupled to the first processor and configured to receive input from a user.

15. The system of claim 13, further comprising a capture device coupled to the first processor and configured to capture visual information.

16. The system of claim 13, wherein at least a third and fourth of the plurality of processors are serially coupled to form a serial processor path.

17. The system of claim 16, further comprising a buffer coupled between the third processor and the fourth processor.

18. The system of claim 13, further comprising a programmable voltage source coupled to the plurality of processors and configured to provide an independent voltage source to the plurality of processors.