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Low power clocking systems and methods

  • US 7,139,921 B2
  • Filed: 06/14/2004
  • Issued: 11/21/2006
  • Est. Priority Date: 03/21/2001
  • Status: Expired due to Term
First Claim
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1. An integrated circuit comprising:

  • a digital portion including;

    a plurality of processors configured to execute one or more algorithms, each of the plurality of processors having a respective clock input to control a rate of processor performance; and

    a controller having a plurality of clock outputs coupled to the respective clock input of the plurality of processors, wherein the controller is configured to vary a clock frequency of at least one of the plurality of processors to control the rate of processor performance; and

    an analog portion coupled to the digital portion, the analog portion including at least one radio frequency (RF) transceiver.

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