Semiconductor device having an impurity gradient in the impurity regions and method of manufacture
First Claim
1. A semiconductor device including a CMOS circuit having an NTFT and a PTFT, each of the NTFT and the PTFT including an active layer, an insulation film in contact with the active layer, and a wiring in contact with the insulation film, whereinonly the NTFT includes a side wall spacer on a side of the wiring, the active layer of the NTFT includes a channel forming region and at least three kinds of impurity regions each containing an element belonging to the group 15 at a different concentration, the impurity region in contact with the channel forming region among the three kinds of impurity regions overlaps by way of the insulation film with the side wall, the active layer of the PTFT includes a channel forming region and two kinds of impurity regions each containing an element belonging to the group 13 at an identical concentration, and an element used for crystallization of the active layer of the NTFT and the active layer of the PTFT is present at a concentration of 1×
- 1017 to 1×
1020 atoms/cm3 in one of the impurity region most remote from the channel forming region of the NTFT and in one of the impurity region most remote from the channel forming region of the PTFT.
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Accused Products
Abstract
The active layer of an n-channel TFT is formed with a channel forming region, a first impurity region, a second impurity region and a third impurity region. In this case, the concentration of the impurities in each of the impurity regions is made higher as the region is remote from the channel forming region. Further, the first impurity region is disposed so as to overlap a side wall, and the side wall is caused to function as an electrode to thereby attain a substantial gate overlap structure. By adopting the structure, a semiconductor device of high reliability can be manufactured.
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Citations
63 Claims
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1. A semiconductor device including a CMOS circuit having an NTFT and a PTFT, each of the NTFT and the PTFT including an active layer, an insulation film in contact with the active layer, and a wiring in contact with the insulation film, wherein
only the NTFT includes a side wall spacer on a side of the wiring, the active layer of the NTFT includes a channel forming region and at least three kinds of impurity regions each containing an element belonging to the group 15 at a different concentration, the impurity region in contact with the channel forming region among the three kinds of impurity regions overlaps by way of the insulation film with the side wall, the active layer of the PTFT includes a channel forming region and two kinds of impurity regions each containing an element belonging to the group 13 at an identical concentration, and an element used for crystallization of the active layer of the NTFT and the active layer of the PTFT is present at a concentration of 1× - 1017 to 1×
1020 atoms/cm3 in one of the impurity region most remote from the channel forming region of the NTFT and in one of the impurity region most remote from the channel forming region of the PTFT. - View Dependent Claims (5, 6, 7, 8, 9, 13, 14, 15)
- 1017 to 1×
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2. A semiconductor device having a CMOS circuit having an NTFT and a PTFT, each of the NTFT and the PTFT including an active layer, an insulation film in contact with the active layer and a wiring in contact with the insulation film, wherein
only the NTFT includes a side wall spacer on a side of the wiring, the active layer of the NTFT includes a structure in which a channel forming region, a first impurity region, a second impurity region and a third impurity region are arranged in this order, each of the first impurity region, the second impurity region and the third impurity region contains an element belonging to the group 15 at a different concentration, the first impurity region overlaps by way of the insulation film with the side wall, the active layer of the PTFT includes a structure in which a channel forming region, a fourth impurity region and a fifth impurity region are arranged in this order, each of the fourth impurity region and the fifth impurity region contains an element belonging to the group 13 at an identical concentration and an element used for the crystallization of the active layer is present at a concentration of 1× - 1017 to 1×
1020 atoms/cm3 in the third impurity region and the fifth impurity region,. - View Dependent Claims (10, 11, 12)
- 1017 to 1×
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3. A semiconductor device having a CMOS circuit having an NTFT and a PTFT each of the NTFT and the PTFT including an active layer, an insulation film in contact with the active layer and a wiring in contact with the insulation film, wherein
only the NTFT includes a side wall spacer on a side of the wiring, the active layer of the NTFT includes a channel forming region and at least three kinds of impurity regions each containing an element belonging to the group 15 at a different concentration, the concentration of the element belonging to the group 15 is higher as the distance from the channel forming region is greater in at least three kinds of impurity regions, the active layer of PTFT includes a channel forming region and two kinds of impurity regions containing an element belonging to the group 13 at an identical concentration, and the active layer of PTFT includes a channel forming region and two kinds of impurity regions containing an element belonging to the group 13 at an identical concentration, and in which an element used for the crystallization of the active layer is present at a concentration of 1× - 1017 to 1×
1020 atoms/cm3 in the impurity region most remote from the channel forming region of the NTFT and in the impurity region most remote from the channel forming region of the PTFT.
- 1017 to 1×
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4. A semiconductor device including a CMOS circuit having an NTFT and a PTFT each of the NTFT and the PTFT including an active layer, an insulation film in contact with the active layer and a wiring in contact with the insulation film, wherein
only the NTFT includes a side wall spacer on a side of the wiring, the active layer of the NTFT has a structure in which a channel forming region, a first impurity region, a second impurity region and a third impurity region are arranged in this order, each of the first impurity region, the second impurity region and the third impurity region contains identical impurities at a different concentration, the concentration of the impurities is higher in the order of the first impurity region, the second impurity region and the third impurity region, the active layer of the PTFT has a structure in which a channel forming region, a fourth impurity region and a fifth impurity region are arranged in this order, each of the fourth impurity region and the fifth impurity region contains an element belonging to the group 13 at an identical concentration, and an element used for the crystallization of the active layer of the NTFT and the active layer of the PTFT is present at a concentration of 1× - 1017 to 1×
1020 atoms/cm3 in the third impurity region and the fifth impurity region.
- 1017 to 1×
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16. A semiconductor device comprising:
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a semiconductor film formed on an insulating surface;
a channel forming region in the semiconductor film;
a gate insulating film formed on the semiconductor film;
a gate electrode formed over the channel forming region with the gate insulating film interposed therebetween;
a pair of side walls adjacent to side surfaces of the gate electrode;
an insulating film on the gate electrode and the pair of side walls;
a pair of first impurity regions doped with an N-type impurity at a first concentration and formed in the semiconductor film with the channel forming region extending therebetween wherein the pair of side walls overlap only the pair of first impurity regions; and
a pair of second impurity regions doped with an N-type impurity at a second concentration greater than the first concentration and formed in the semiconductor film adjacent to the pair of first impurity region; and
a pair of third impurity regions doped with an N-type impurity at a third concentration greater than the second concentration and formed in the semiconductor film with the pair of second regions extending between the channel forming region and the pair of third impurity regions, wherein the pair of side walls do not overlap the pair of second impurity regions and third impurity regions. - View Dependent Claims (17, 18, 19, 20, 21)
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22. A semiconductor device comprising:
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a semiconductor film formed on an insulating surface;
a channel forming region in the semiconductor film;
a gate insulating film formed on the semiconductor film;
a gate electrode formed over the channel forming region with the gate insulating film interposed therebetween;
a pair of conductive side walls adjacent to side surfaces of the gate electrode;
an insulating film on the gate electrode and the pair of conductive side walls;
a pair of first impurity regions doped with an N-type impurity at a first concentration and formed in the semiconductor film with the channel forming region extending therebetween wherein the pair of side walls overlap only the pair of first impurity regions; and
a pair of second impurity regions doped with an N-type impurity at a second concetration greater than the first concentration and formed in the semiconductor film adjacent to the pair of first impurity regions; and
a pair of third impurity regions doped with an N-type impurity at a third concentration greater than the second concentration and formed in the semiconductor film with the pair of second impurity regions extending between the channel forming region and the pair of third impurity region, wherein the pair of side walls do not overlap the pair of second impurity regions and third impurity regions. - View Dependent Claims (23, 24, 25, 26, 27)
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28. A semiconductor device comprising:
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(a) a thin film transistor over a substrate, said thin film transistor comprising;
a semiconductor film formed on an insulating surface;
a channel forming region in the semiconductor film;
a gate insulating film formed on the semiconductor film;
a gate electrode formed over the channel forming region with the gate insulating film interposed therebetween;
a pair of side walls adjacent to side surfaces of the gate electrode;
an insulating film on the gate electrode and the pair of side walls;
a pair of first impurity regions doped with an N-type impurity at a first concentration and formed in the semiconductor film with the channel forming region extending therebetween wherein the pair of side walls overlap only the pair of first impurity regions; and
a pair of second impurity regions doped with an N-type impurity at a second concentration greater than the first concentration and formed in the semiconductor film adjacent to the pair of first impurity regions; and
a pair of third impurity regions doped with an N-type impurity at a third concentration greater than the second concentration and formed in the semiconductor film with the pair of second impurity regions extending between the channel forming region and the pair of third impurity regions, wherein the pair of side walls do not overlap the pair of second impurity regions and third impurity regions;
(b) an interlayer insulating film formed over the thin film transistor; and
(c) a pixel electrode formed over the interlayer insulating film and electrically connected to one of the third impurity regions. - View Dependent Claims (29, 30, 31, 32, 33)
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34. A semiconductor device comprising:
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(a) a thin film transistor formed over a substrate, said thin film transistor comprising;
a semiconductor film formed on an insulating surface;
a channel forming region in the semiconductor film;
a gate insulating film formed on the semiconductor film;
a gate electrode formed over the channel forming region with the gate insulating film interposed therebetween;
a pair of side walls adjacent to side surfaces of the gate electrode;
an insulating film on the gate electrode and the pair of side walls;
a pair of first impurity regions doped with an N-type impurity at a first concentration and formed in the semiconductor film with the channel forming region extending therebetween wherein the pair of side walls overlap only the pair of first impurity regions; and
a pair of second impurity regions doped with an N-type impurity at a second concentration greater than the first concentration and formed in the semiconductor film adjacent to the pair of first impurity regions; and
a pair of third impurity regions doped with an N-type impurity at a third concentration greater than the second concentration and formed in the semiconductor film with the pair of second impurity regions extending between the channel forming region and the pair of third impurity regions, wherein the pair of side walls do not overlap the pair of second impurity regions and third impurity regions;
(b) an interlayer insulating film formed over the thin film transistor; and
(c) a pixel electrode formed over the interlayer insulating film and electrically connected to one of the third impurity regions. - View Dependent Claims (35, 36, 37, 38, 39)
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40. A semiconductor device comprising:
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a semiconductor film formed on an insulating surface;
a channel forming region in the semiconductor film;
a gate insulating film formed on the semiconductor film;
a gate electrode formed over the channel forming region with the gate insulating film interposed therebetween;
a second insulating film in contact with an upper surface and side surfaces of the gate electrode;
a pair of side walls adjacent to the side surfaces of the gate electrode with the second insulating film interposed therebetween;
a pair of first impurity regions doped with an N-type impurity at a first concentration and formed in the semiconductor film with the channel forming region extending therebetween wherein the pair of side walls overlap only the pair of first impurity regions;
a pair of second impurity regions doped in an N-type impurity at a second concentration greater than the first concentration and formed in the semiconductor film adjacent to the pair of first impurity regions; and
a pair of third impurity regions doped with an N-type impurity at a third concentration greater than the second concentration and formed in the semiconductor film with the pair of second impurity regions extending between the channel forming region and the pair of third impurity regions, wherein the pair of side walls do not overlap the pair of second impurity regions and third impurity regions. - View Dependent Claims (41, 42, 43, 44, 45)
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46. A semiconductor device comprising:
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(a) a thin film transistor over a substrate, said thin film transistor comprising;
a semiconductor film formed on an insulating surface;
a channel forming region in the semiconductor film;
a gate insulating film formed on the semiconductor film;
a gate electrode formed over the channel forming region with the gate insulating film interposed therebetween;
a second insulating film in contact with an upper surface and side surfaces of the gate electrode;
a pair of side walls adjacent to side surfaces of the gate electrode with the second insulating film interposed therebetween;
a pair of first impurity regions doped with an N-type impurity at a first concentration and formed in the semiconductor film with the channel forming region extending therebetween wherein the pair of side walls overlap only the pair of first impurity regions; and
a pair of second impurity regions doped with an N-type impurity at a second concentration greater than the first concentration and formed in the semiconductor film adjacent to the pair of first impurity regions; and
a pair of third impurity regions doped with an N-type impurity at a third concentration greater than the second concentration and formed in the semiconductor film with the pair of second impurity regions extending between the channel forming region and the pair of third impurity regions, wherein the pair of side walls do not overlap the pair of second impurity regions and third impurity regions;
(b) an interlayer insulating film formed over the thin film transistor; and
(c) a pixel electrode formed over the interlayer insulating film and electrically connected to one of the third impurity regions. - View Dependent Claims (47, 48, 49, 50, 51)
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52. A semiconductor device comprising a CMOS circuit comprising:
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an NTFT having;
a first semiconductor film formed on an insulating surface;
a first channel forming region in the first semiconductor film;
a first gate insulating film formed on the first semiconductor film;
a first gate electrode formed over the first channel forming region with the first gate insulating film interposed therebetween;
a pair of side walls adjacent to side surfaces of the first gate electrode;
a second insulating film on the first gate electrode and the pair of side walls; and
a PTFT having;
a second semiconductor film formed on an insulating surface;
a second channel forming region in the second semiconductor film;
a third gate insulating formed on the second semiconductor film;
a second gate electrode formed over the second channel forming region with the third gate insulating film interposed therebetween;
wherein a pair of first impurity regions doped with an N-type impurity at a first concentration and formed in the first semiconductor film with the first channel forming region extending therebetween wherein the pair of side walls overlap only the pair of first impurity regions;
wherein a pair of second impurity regions doped with an N-type impurity at a second concentration greater than the first concentration and formed in the first semiconductor film adjacent to the pair of first impurity regions; and
wherein a pair of third impurity regions doped with an N-type impurity at a third concentration greater than the second concentration and formed in the first semiconductor film with the pair of second impurity regions extending between the first channel forming region and the pair of third impurity regions, wherein the pair of side walls do not overlap the pair of second impurity regions and third impurity regions. - View Dependent Claims (53, 54, 55, 56, 57)
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58. A semiconductor device comprising a CMOS circuit comprising:
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an NTFT having;
a first semiconductor film formed on an insulating surface;
a first channel forming region in the first semiconductor film;
a first gate insulating film formed on the first semiconductor film;
a first gate electrode formed over the first channel forming region with the first gate insulating film interposed therebetween;
a second insulating film in contact with an upper surface and side surfaces of the first gate electrode;
a pair of side walls adjacent to side surfaces of the first gate electrode with the second insulating film interposed therebetween; and
a PTFT having;
a second semiconductor film formed on an insulating surface;
a second channel forming region in the second semiconductor film;
a third gate insulating formed on the second semiconductor film;
a second gate electrode formed over the second channel forming region with the third gate insulating film interposed therebetween;
wherein a pair of first impurity regions doped with an N-type impurity at a first concentration and formed in the first semiconductor film with the first channel forming region extending therebetween wherein the pair of side walls overlap only the pair of first impurity regions;
wherein a pair of second impurity regions doped with an N-type impurity at a second concentration greater than the first concentration and formed in the first semiconductor film adjacent to the pair of first impurity regions; and
wherein a pair of third impurity regions doped with an N-type impurity at a third concentration greater than the second concentration and formed in the first semiconductor film with the pair of second impurity regions extending between the first channel forming region and the pair of third impurity regions, wherein the pair of side walls do not overlap the pair of second impurity regions and third impurity regions. - View Dependent Claims (59, 60, 61, 62, 63)
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Specification