Method and structure for buried circuits and devices

• US 7,141,853 B2
• Filed: 04/27/2004
• Issued: 11/28/2006
• Est. Priority Date: 06/12/2001
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Campbell, John E., Srikrishnan, Kris V., Devine, William T.
• Primary Examiner(s): Quach, T. N.
• Application Number:
  US10/832,894
• Publication Number:
  US 20050029592A1
• Time in Patent Office: 945 Days
• Field of Search: 257/347, 257/351
• US Class Current: 257/347
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/76251 using bonding techniques
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/11803 using field effect technology
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78612 for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/373 the capacitor extending under or around the transistor

Abstract

A method and structure for fabricating an electronic device using an SOI technique that results in formation of a buried oxide layer. The method includes fabricating at least one first component of the electronic device and fabricating at least one second component of the electronic device, wherein the first component and the second component are on opposite sides of the buried oxide layer, thereby causing the buried oxide layer to perform a function within the electronic device.

Entire circuits can be designed around this technique.

Claims

1. An electronic circuit provided in a semiconductor-on-insulator (SOI) substrate, comprising:

a plurality of interconnected field effect transistors (FETs) having elements disposed in a device layer overlying a buried oxide layer of the SOI substrate, wherein at least one of the interconnected FETs includes a portion of the buried oxide layer as a functional element integral to its operation, wherein the electronic curcuit comprises a complementary metal oxide semiconductor (CMOS) NOR circuit.

2. The electronic circuit of claim 1, wherein the CMOS NOR circuit is provided on a semiconductor-on-insulator (SOI) substrate having a buried oxide layer and a device layer disposed above the buried oxide layer, the CMOS NOR circuit comprising:

a first p-type field effect transistor (PFET) and a second PFET connected in series, the first and second PFETs each having a source terminal, a drain terminal and a gate terminal, wherein the source terminal of the first PFET is coupled to receive a supply voltage;

a first n-type field effect transistor (NFET) and a second NFET connected in parallel, the first and second NFETs having a common drain terminal and a common source terminal, wherein the common source terminal of the first and second NFETs is coupled for providing a connection to ground.

wherein the drain terminal of the second PFET is connected to the common drain terminal of the first and second NFETs, and the gate electrodes of the first and second NFETs are disposed on opposite sides of the buried oxide layer.

3. The electronic circuit of claim 2, wherein the gate electrodes of the first PFET and the second NFET are coupled to receive a first input signal, the gate electrodes of the second PFET and the first NFET are coupled to receive a second input signal, and the common drain terminal of the first and second NFETs is coupled to provide a NOR function output in accordance with the first and second FETs.

4. The electronic circuit of claim 2, wherein the first and second PFETs are both disposed above the buried oxide layer.

5. A semiconductor structure provided on a semiconductor-on-insulator (SOI) substrate, comprising:

a first single crystal semiconductor region disposed above the SOI substrate;

a gate electrode disposed in the first single crystal semiconductor region;

a buried oxide layer disposed below the first single crystal semiconductor region;

a second single crystal semiconductor region disposed below the buried oxide layer;

a buried element disposed In the second single crystal semiconductor region; and

an insulator layer disposed adjacent to at least one sidewall surface of the buried element.

6. The semiconductor structure of claim 5, wherein the insulator layer is also disposed adjacent to a bottom surface of the buried element.

7. The semiconductor structure of claim 5, wherein the buried element comprises an element selected from the group consisting of a buried gate, a body contact, a buried wire, and a buried capacitor.

8. The semiconductor structure of claim 7, wherein a region of the buried oxide layer located between the first single crystal semiconductor region and the buried gate includes a thin region, the thin region adapted to perform a function integral to the buried gate.

9. The semiconductor structure of claim 7, wherein a top surface of the body contact directly contacts the first single crystal semiconductor region.

10. The semiconductor structure of claim 7, further comprising at least one conducting via extending from an upper surface of the buried wire through the buried oxide layer to a top surface of the first single crystal semiconductor region.

11. The semiconductor structure of claim 5, wherein the buried element comprise a material selected from the group consisting of polysilicon, doped polysilicon, a refractory conductor, tungsten, and polycide.