Delay locked loop (DLL) using an oscillator and a counter and a clock synchronizing method

• US 7,142,027 B2
• Filed: 01/18/2005
• Issued: 11/28/2006
• Est. Priority Date: 01/28/2004
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Jang-Sub, Jeon, Yong-Weon
• Primary Examiner(s): LE, DINH THANH
• Application Number:
  US11/037,484
• Publication Number:
  US 20050162204A1
• Time in Patent Office: 679 Days
• Field of Search: 327156-159, 327147-150, 327/153, 327/161
• US Class Current: 327/158
• CPC Class Codes: H03L 7/00 Automatic control of frequency or phase; Synchronisation

Abstract

Provided are a delay locked loop (DLL) using an oscillator and a counter and a clock synchronizing method. The DLL converts cycle information of an input clock signal into digital information using the oscillator and the counter and generates output clock signals from the input clock signal using the digital information after a predetermined delay time elapses. The output clock signals each have a duty cycle of 50%. The DLL includes: a time-to-digital converter for converting one period (T) of the input clock signal into a digital signal to generate coarse cycle information signals and fine cycle information signals; a first cycle delay unit for generating a first cycle clock signal delayed by T/2 from an internal clock signal and half cycle information signals in response to the coarse cycle information signals and the fine cycle information signals; a second cycle delay unit for generating a second cycle clock signal delayed by T/4 from the input clock signal in response to the coarse cycle information signals and half cycle information signals; and a clock recovery unit for generating the output clock signals in response to the first and second cycle clock signals.

Claims

1. A delay locked loop (DLL) comprising:

a time-to-digital converter for receiving an input clock signal and converting a period (T) of the input clock signal into a digital signal to generate coarse cycle information signals and fine cycle information signals;

a first cycle delay unit for generating a first cycle clock signal delayed by T/2 from an internal clock signal and half cycle information signals in response to the coarse cycle information signals and fine cycle information signals;

a second cycle delay unit for generating a second cycle clock signal delayed by T/4 from the input clock signal in response to the coarse cycle information signals and half cycle information signals; and

a clock recovery unit for generating the internal clock signal and output clock signals in response to the first and second cycle clock signals.

2. The DLL as claimed in claim 1, wherein the time-to-digital converter comprises:

an oscillator for receiving one cycle of the input clock signal to generate the fine cycle information signals; and

a counter for counting pulses output from the oscillator to generate the coarse cycle information signals.

3. The DLL as claimed in claim 2, wherein the oscillator comprises:

a plurality of delay cells connected in serial, wherein the input clock signal is input to a first delay cell, and an output of the last delay cell is input to the counter and the first delay cell.

4. The DLL as claimed in claim 1, wherein the first cycle delay unit comprises:

an oscillator for receiving the coarse cycle information signals, the fine cycle information signals and the internal clock signal to generate the half cycle information signals; and

a counter for generating the first cycle clock signal in response to the output of the oscillator and the coarse cycle information signals.

5. The DLL as claimed in claim 4, wherein the oscillator comprises:

a plurality of delay cells connected in serial, wherein the internal clock signal is input to a first delay cell, an output of a last delay cell is input to the counter and the first delay cell, and the half cycle information signals and the number of the plurality of delay cells processing the signals are set based on the a value of the least significant bit of the coarse cycle information signals.

6. The DLL as claimed in claim 5, wherein the oscillator begins to operate after the delay time of the plurality of delay cells has elapsed.

7. The DLL as claimed in claim 1, wherein the second cycle delay unit comprises:

an oscillator for receiving the coarse cycle information signals, the half cycle information signals and the input clock signal to generate quad cycle information signals; and

a counter for generating the second cycle clock signal in response to an output of the oscillator and the quad cycle information signals.

8. The DLL as claimed in claim 7, wherein the oscillator comprises:

a plurality of delay cells connected in serial, wherein the input clock signal is input to a first delay cell, an output of a last delay cell is input to the counter and the first delay cell, and the quad cycle information signals and the number of the plurality of delay cells processing the signals are set based on a value of the least significant bit-1 of the coarse cycle information signals.

9. The DLL as claimed in claim 8, wherein the oscillator begins to operate after the delay time of the plurality of delay cells has elapsed.

10. The DLL as claimed in claim 1, wherein the output clock signals generated by the clock recovery unit are delayed by T/4 from the input clock signal and have a duty cycle of 50%.

11. A delay locked loop (DLL) comprising:

a time-to-digital converter for receiving an input clock signal and converting a period (T) of the input clock signal into a digital value to generate coarse cycle information signals and fine cycle information signals;

a first cycle delay unit for receiving the coarse cycle information signals, the fine cycle information signals and an internal clock signal, to generate a first clock signal delayed by a first delay time from the internal clock signal and a first cycle information signal;

a second cycle delay unit for receiving the coarse cycle information signals, the first cycle information signal and the input clock signal, to generate a second clock signal delayed by a second delay time from the input clock signal; and

a clock recovery unit for receiving the first and second clock signals to generate output clock signals that are delayed by the first delay time from the internal clock signal and the input clock signal and have a duration corresponding to the second delay time.

12. The DLL as claimed in claim 11, wherein the time-to-digital converter comprises:

an oscillator comprising a plurality of delay cells for receiving one cycle of the input clock signal to generate the fine cycle information signals, which are output from the plurality of delay cells, and a first turn signal; and

a counter for counting pulses of the first turn signal to generate the coarse cycle information signals.

13. The DLL as claimed in claim 11, wherein the first cycle delay unit comprises:

an oscillator comprising a plurality of delay cells for receiving the internal clock signal and generating half cycle information signals and a second turn signal in response to the coarse cycle information signals and the fine cycle information signals; and

a counter for generating the first cycle clock signal in response to the second turn signal and the coarse cycle information signals.

14. The DLL as claimed in claim 13, wherein the oscillator sets the half cycle information signals and the number of the plurality of delay cells processing the signals based on the a value of the least significant bit of the coarse cycle information signals.

15. The DLL as claimed in claim 11, wherein the second cycle delay unit comprises:

an oscillator comprising a plurality of delay cells for receiving the input clock signal and generating quad cycle information signals and a third turn signal in response to the coarse cycle information signals and the half cycle information signals; and

a counter for generating the second cycle clock signal in response to the third turn signal and the quad cycle information signals.

16. The DLL as claimed in claim 15, wherein the oscillator sets the quad cycle information signals and the number of the plurality of delay cells processing the signals based on the a value of the least significant bit-1 of the coarse cycle information signals.

17. The DLL as claimed in claim 11, wherein the first delay time is T/2 and the second delay time is T/4.

18. A clock synchronizing method comprising:

receiving an input clock signal and converting a period (T) of the input clock signal into a digital signal to generate coarse cycle information signals and fine cycle information signals;

generating a first cycle clock signal delayed by a first delay time from an internal clock signal and half cycle information signals in response to the coarse cycle information signals and the fine cycle information signals;

generating a second cycle clock signal delayed by a second delay time from the input clock signal in response to the coarse cycle information signals and the fine cycle information signals;

generating the internal clock signal delayed by the first delay time from the input clock signal in response to the first and second cycle clock signals; and

generating output clock signals delayed by the second delay time from the input clock signal the output clock signals having a duration corresponding to the second cycle time in response to the first and second cycle clock signals.

19. The clock synchronizing method as claimed in claim 18, wherein the first delay time is T/2 and the second delay time is T/4.

20. The clock synchronizing method as claimed in claim 18, wherein the step of receiving an input clock signal and converting a period (T) of the input clock signal to generate coarse cycle information signals and fine cycle information signals comprises:

receiving one cycle of the input clock signal via an oscillator comprising a plurality of delay cells and generating the fine cycle information signals and a first turn signal as outputs of the plurality of delay cells; and

generating the coarse cycle information signals with a counter for counting pulses of the first turn signal.

21. The clock synchronizing method as claimed in claim 18, wherein the step of generating a first cycle clock signal delayed by a first delay time from an internal clock signal and a half cycle information signal in response to the coarse cycle information signals and the fine cycle information signals comprises:

receiving the internal clock signal via an oscillator comprising a plurality of delay cells, generating the half cycle information signals as outputs of the plurality of delay cells, and generating a second turn signal in response to the coarse cycle information signals and the fine cycle information signals; and

generating the first cycle clock signal in response to the coarse cycle information signals with a counter for counting pulses of the second turn signal.

22. The clock synchronizing method as claimed in claim 21, wherein the oscillator sets the half cycle information signals and the number of the plurality of delay cells processing the signals based on a value of the least significant bit of the coarse cycle information signals.

23. The clock synchronizing method as claimed in claim 18, wherein the step of generating a second cycle clock signal delayed by a second delay time from the input clock signal in response to the coarse cycle information signals and the fine cycle information signals comprises:

receiving the input clock signal via an oscillator including a plurality of delay cells and generating quad cycle information signals and a third turn signal in response to the coarse cycle information signals and the half cycle information signals; and

generating the second cycle clock signal in response to the quad cycle information signals with a counter for counting the third turn signal.

24. The clock synchronizing method as claimed in claim 23, wherein the oscillator sets the quad cycle information signals and the number of the plurality of delay cells processing the signals based on a value of the least significant bit-1 of the coarse cycle information signals.