Method and apparatus for incorporating block redundancy in a memory array
First Claim
1. A method for implementing block redundancy in an integrated circuit memory array, said method comprising:
- mapping the array lines of a defective block of a first type into a spare block of the same type;
mapping array lines of a first adjacent block which are shared with array lines of the defective block, and mapping array lines of a second adjacent block which are shared with array lines of the defective block, into a second spare block of a second type, thereby mapping the defective block and portions of both adjacent blocks into just two spare blocks.
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Accused Products
Abstract
An integrated circuit memory array includes alternating first and second types of memory blocks, each memory block including respective array lines shared with a respective array line in an adjacent memory block. The array lines of a defective block of one type are mapped into a spare block of the same type. The array lines of a first adjacent block which are shared with array lines of the defective block, and the array lines of a second adjacent block which are shared with array lines of the defective block, are mapped into a second spare block of the other type, thereby mapping the defective block and portions of both adjacent blocks into just two spare blocks.
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Citations
40 Claims
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1. A method for implementing block redundancy in an integrated circuit memory array, said method comprising:
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mapping the array lines of a defective block of a first type into a spare block of the same type; mapping array lines of a first adjacent block which are shared with array lines of the defective block, and mapping array lines of a second adjacent block which are shared with array lines of the defective block, into a second spare block of a second type, thereby mapping the defective block and portions of both adjacent blocks into just two spare blocks. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. An integrated circuit comprising:
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a memory array having alternating first and second types of memory blocks, each memory block including respective array lines shared with a respective array line in an adjacent memory block; mapping circuits, responsive to an address corresponding to a defective block, for mapping the array lines of a defective block of one type into a spare block of the same type, and further for mapping array lines of a first adjacent block which are shared with array lines of the defective block, and mapping array lines of a second adjacent block which are shared with array lines of the defective block, into a second spare block of the other type, thereby mapping the defective block and portions of both adjacent blocks into just two spare blocks. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35)
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36. An integrated circuit comprising:
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a memory array; a first plurality of lines of a first type associated with a first portion of the memory array; a second plurality of lines of the first type associated with a second portion of the memory array; a third plurality of lines of the first type associated with a spare portion of the memory array; said third plurality of lines being respectively coupled to either the first or second plurality of lines when said spare portion of the memory array is utilized, and coupled to neither the first or second plurality of lines when said spare portion of the memory array is not utilized. - View Dependent Claims (37, 38, 39, 40)
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Specification