Method and apparatus for shared processing a plurality of signals

• US 7,142,606 B2
• Filed: 09/27/2002
• Issued: 11/28/2006
• Est. Priority Date: 09/27/2002
• Status: Active Grant

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Talwalkar, Sumit Anil, Sobchak, Charles Leroy, Rahman, Mahibur
• Primary Examiner(s): Tran, Khai
• Assistant Examiner(s): Ware, Cicely
• Application Number:
  US10/256,906
• Publication Number:
  US 20040066803A1
• Time in Patent Office: 1,523 Days
• Field of Search: 375/259, 768/317, 341143-155
• US Class Current: 375/259
• CPC Class Codes: H03M 3/474 using time-division multiplexing

Abstract

A signal processing apparatus preferably suitable for implementation as an integrated circuit, that is arranged and constructed to be shared for processing a plurality of signals without interference between the signals and method thereof, the signal processing apparatus comprising: an input multiplexer for sequentially selecting from among the plurality of signals to provide a sequence of selected signals; a processing unit for processing the sequence of selected signals to provide a sequence of processed signals, the processing unit having an input coupled to the input multiplexer and a delay stage including a plurality of series coupled delay elements with one delay element corresponding to each of the plurality of signals; and an output de-multiplexer for sequentially selecting from the sequence of processed signals to provide a plurality of processed signals corresponding one to one with the plurality of signals.

Claims

1. A signal processing apparatus that is arranged and constructed to be shared for processing a plurality of signals without interference between the signals, the signal processing apparatus comprising:

an input multiplexer for sequentially selecting from among the plurality of signals to provide a sequence of selected signals at a first sample rate;

a processing unit for concurrently processing the sequence of selected signals to provide a sequence of processed signals at a second sample rate that differs from the first sample rate, the processing unit having an input coupled to the input multiplexer and a delay stage including a number of series coupled delay elements with the number of delay elements corresponding to the plurality of signals;

an output de-multiplexer for sequentially selecting from the sequence of processed signals at the second sample rate to provide a plurality of processed signals corresponding one to one with the plurality of signals; and

a controller for synchronizing the input multiplexer, the processing unit, and the output de-multiplexer so that the plurality of processed signals correspond one to one with the plurality of signals.

2. The signal processing apparatus of claim 1 wherein said processing unit further includes a sigma delta analog to digital converter (ADC), including the delay stage, for converting the sequence of selected signals from a sequence of sampled signals to a sequence of corresponding digital signals that are said sequence of processed signals.

3. The signal processing apparatus of claim 2 further including a down-sampler that selects a portion of the sequence of corresponding digital signals to be said sequence of processed signals, the portion being a fraction of the sequence of corresponding digital signals and including an equal representation from each of the corresponding digital signals.

4. The signal processing apparatus of claim 3 further including a decimation filter having an input coupled to the sequence of corresponding digital signals, an output coupled to the down-sampler, and a filter delay stage including a plurality of series coupled filter delay elements with a filter delay element corresponding to each of the plurality of signals, the decimation filter for filtering the sequence of corresponding digital signals to limit frequency components of the sequence of corresponding digital signals before selecting the portion of the sequence of corresponding digital signals.

5. The signal processing apparatus of claim 1 wherein said processing unit further includes a sigma delta based modulator having the delay stage and noise shaping properties for converting the sequence of selected signals from a sequence of sampled signals to a sequence of corresponding digital signals that have been filtered.

6. The signal processing apparatus of claim 5 wherein said sigma delta based modulator is for converting the sequence of selected signals from a sequence of sampled signals to a sequence of corresponding digital signals that have been one of low pass, high pass, and band pass filtered.

7. The signal processing apparatus of claim 1 wherein said input multiplexer sequentially selects from the plurality of signals corresponding to one of two unique multiple access signals, a complex signal having in phase and quadrature components, spatial diversity signals, and temporal diversity signals.

8. The signal processing apparatus of claim 1 wherein the delay stage is one of a plurality of series coupled flip-flops, a shift register, and a plurality of series coupled switched capacitor delays.

9. A method of processing a plurality of signals without interference between the signals using a shared processor, the method comprising:

providing, at a first sample rate, a sequence of selected signals corresponding to the plurality of signals;

process, concurrently, the sequence of selected signals to provide a sequence of processed signals at a second sample rate that differs from the first sample rate, the processing including

delaying a linear combination of each of the sequence of selected signals using a delay stage including a plurality of series coupled delay elements with a delay element corresponding to each of the plurality of signals; and

sequentially and synchronously with the providing the sequence of processed signals at the second sample rate, selecting from the sequence of processed signals to provide a plurality of processed signals corresponding one to one with the plurality of signals.

10. The method of claim 9 wherein said processing the sequence of selected signals further includes

converting the sequence of selected signals from a sequence of sampled signals to a sequence of corresponding digital signals that are said sequence of processed signals using a sigma delta analog to digital converter.

11. The method of claim 10 further including down-sampling the sequence of corresponding digital signals by selecting a portion of the sequence of corresponding digital signals to be said sequence of processed signals, the portion being a fraction of the sequence of corresponding digital signals and including an equal representation from each of the corresponding digital signals.

12. The method of claim 11 further including filtering the sequence of corresponding digital signals, using a decimation filter having a filter delay stage including a plurality of series coupled filter delay elements with one filter delay element corresponding to each of the plurality of signals, to limit frequency components of the sequence of corresponding digital signals before selecting the portion of the sequence of corresponding digital signals.

13. The method of claim 9 wherein said processing the sequence of selected signals further includes converting the sequence of selected signals from a sequence of sampled signals to a sequence of corresponding digital signals and filtering the sequence of corresponding digital signals using a sigma delta based modulator with noise shaping properties.

14. The method of claim 9 wherein said filtering the sequence of corresponding digital signals further includes one of low pass, high pass, or band pass filtering the sequence of corresponding digital signals.

15. The method of claim 9 wherein said providing a sequence of selected signals further includes selecting from one of two unique multiple access signals, a complex signal having in phase and quadrature components, spatial diversity signals, and temporal diversity signals.

16. The method of claim 9 wherein said delaying a linear combination of each of the sequence of selected signals using a delay stage further includes using one of a plurality of series coupled flip-flops, a shift register, and a plurality of series coupled switched capacitor delays.

17. An integrated circuit that is arranged and constructed to perform shared processing for a plurality of signals without interference between the signals, the integrated circuit comprising:

an input multiplexer for sequentially selecting from among the plurality of signals to provide a sequence of selected signals at a first sample rate;

a processing unit for concurrently processing the sequence of selected signals to provide a sequence of processed signals at a second sample rate that differs from the first sample rate, the processing unit having an input coupled to the input multiplexer and a delay stage including a number of series coupled delay elements with the number of delay element corresponding to the plurality of signals;

an output de-multiplexer for sequentially selecting from the sequence of processed signals at the second sample rate to provide a plurality of processed signals corresponding one to one with the plurality of signals; and

a controller for synchronizing the input multiplexer, the processing unit, and the output de-multiplexer so that the plurality of processed signals correspond one to one with the plurality of signals.

18. The integrated circuit of claim 17 wherein said processing unit further includes a sigma delta analog to digital converter (ADC) for converting the sequence of selected signals to a sequence of corresponding digital signals that are said sequence of processed signals.

19. The integrated circuit of claim 17 wherein said processing unit further includes a sigma delta digital to analog converter (DAC), an up sampler, and an interpolation filter for converting the sequence of selected signals into the plurality of processed signals corresponding to a sampled analog version of the plurality of signals.

20. The integrated circuit of claim 18 further including a down-sampler that selects a portion of the sequence of corresponding digital signals to be said sequence of processed signals, the portion being a fraction of the sequence of corresponding digital signals and including an equal representation from each of the corresponding digital signals.

21. The integrated circuit of claim 20 further including a decimation filter having an input coupled to the sequence of corresponding digital signals, an output coupled to the down-sampler, and a filter delay stage including a plurality of series coupled filter delay elements with one filter delay element corresponding to each of the plurality of signals, the decimation filter for filtering the sequence of corresponding digital signals to limit frequency components of the sequence of corresponding digital signals before selecting the portion of the sequence of corresponding digital signals.

22. The integrated circuit of claim 17 wherein said processing unit further includes a filter for converting the sequence of selected signals from a sequence of sampled signals to a sequence of corresponding digital signals that have been filtered.

23. The integrated circuit of claim 22 wherein said filter further includes a sigma delta modulator having the delay stage and noise shaping properties having one of a low pass, band pass, and high pass response.

24. The integrated circuit of claim 17 wherein said input multiplexer sequentially selects from the plurality of signals corresponding to one of two unique multiple access signals, a complex signal having in phase and quadrature components, spatial diversity signals, and temporal diversity signals.

25. The integrated circuit of claim 17 wherein the delay stage is one of a plurality of series coupled flip-flops and a shift register and a plurality of series coupled switched capacitor delays.

26. The integrated circuit of claim 17 wherein the processing unit is one of a sigma delta digital to analog converter and an interpolation filter.

27. The integrated circuit of claim 17 the delay stage includes N series coupled delay elements when the plurality of signals is N signals.