Analog unidirectional serial link architecture

• US 7,142,624 B2
• Filed: 09/13/2005
• Issued: 11/28/2006
• Est. Priority Date: 01/16/2001
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Stevens, Joseph Marsh, Cranford, Hayden Clavie Jr., Schmatz, Martin Leo, Norman, Vernon Roberts, Owczarski, Paul Alan, Garvin, Stacy Jean
• Primary Examiner(s): Corrielus, Jean B.
• Application Number:
  US11/225,600
• Publication Number:
  US 20060008042A1
• Time in Patent Office: 441 Days
• Field of Search: 375/371, 375/373, 375/374, 375/375, 375/376, 327/156, 327/147, 327/148, 327/157
• US Class Current: 375/376
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H04L 7/0004 Initialisation of the receiver H04L7/0075 and H04L7/10 take precedence
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

The present analog invention is related to a unified digital architecture comprising logic transmitter portions and logic receiver portions. A unified serial link system and method for transmitting digital data across wired media including a transmitter and a receiver portion is provided, one of the transmitter portion and receiver portion comprising a phase locked loop (PLL) circuit. The PLL circuit comprises a voltage control oscillator, a frequency divider, a phase-frequency detector, a charge pump and a multi-pole loop filter. One embodiment comprises a dual loop PLL having a digital coarse loop and an analog fine loop.

Claims

1. A unified serial link system comprising a transmitter portion and a receiver portion, one of said transmitter portion and said receiver portion comprising a phase locked loop circuit control loop, the circuit control loop comprising:

a voltage control oscillator configured to generate a voltage control oscillator signal and a phase locked loop output signal responsive to a control voltage signal;

a frequency divider connected to the voltage control oscillator to receive the voltage control oscillator signal, the frequency divider configured to generate a frequency divider output;

a phase-frequency detector connected to the frequency divider and configured to receive the frequency divider output and generate a phase-frequency detector output;

a charge pump connected to the phase-frequency detector and configured to receive the phase-frequency detector output and generate a charge pump output; and

a multi-pole loop filter connected to the charge pump and the voltage control oscillator, the multi-pole loop filter configured to receive the charge pump output and generate the control voltage signal to the voltage control oscillator;

wherein the voltage control oscillator is further configured to generate the voltage control oscillator signal and the phase locked loop output signal responsive to a coarse control voltage signal, and the phase locked loop control circuit further comprises a coarse loop, said coarse loop comprising;

a voltage comparator connected to the multi-pole loop filter and configured to receive the control voltage signal;

a reference generator connected to the voltage comparator and configured to generate a reference signal;

wherein said voltage comparator generates a comparator output from the control voltage signal and the reference signal;

a phase locked loop control logic circuit connected to the comparator configured to sample the comparator output and generate a control logic output;

a digital to analog converter connected to the phase locked loop control logic circuit and configured to receive the control logic output and generate a control voltage output; and

a low pass filter connected to the digital to analog converter and to the voltage control oscillator and configured to receive the control voltage output and generate the coarse control voltage signal.

2. A unified serial link system comprising a transmitter portion and a receiver portion, the transmitter portion comprising a dual-loop phase locked loop circuit control loop, the circuit control loop comprising:

a first loop voltage control oscillator configured to generate a first loop voltage control oscillator signal and a phase locked loop output signal responsive to a control voltage signal;

a first loop frequency divider connected to the first loop voltage control oscillator to receive the first loop voltage control oscillator signal, the first loop frequency divider configured to generate a first loop frequency divider output;

a first loop phase-frequency detector connected to the first loop frequency divider and a second loop frequency divider and configured to receive the first loop frequency divider output and a second loop frequency divider output and generate a first loop phase-frequency detector output;

a first loop charge pump connected to the first loop phase-frequency detector and configured to receive the first loop phase-frequency detector output and generate a first loop charge pump output;

a first loop multi-pole loop filter connected to the first loop charge pump and the first loop voltage control oscillator, the first loop multi-pole loop filter configured to receive the first loop charge pump output and generate the first loop control voltage signal to the first loop voltage control oscillator;

a second loop phase-frequency detector connected to the second loop frequency divider and configured to receive the second loop frequency divider output and generate a second loop phase-frequency detector output;

a second loop charge pump connected to the second loop phase-frequency detector and configured to receive the second loop phase-frequency detector output and generate a second loop charge pump output;

a second loop multi-pole loop filter connected to the second loop charge pump and configured to receive the second loop charge pump output and generate a second loop voltage signal;

a LC oscillator connected to the second loop multi-pole loop filter and configured to generate a LC signal to the second loop frequency divider and the first loop phase-frequency detector responsive to the second loop multi-pole loop filter voltage signal;

a transmitter phase buffer circuit connected to the circuit control loop and configured to receive and re-power the phase locked loop output signal; and

a transmitter finite impulse response equalization driver circuit connected to said phase buffer circuit to receive said re-powered phase locked loop output signal.

3. A unified serial link system comprising a transmitter portion and a receiver portion, said receiver portion comprising a phase locked loop circuit control loop, the circuit control loop comprising:

a voltage control oscillator configured to generate a voltage control oscillator signal and a phase locked loop output signal responsive to a control voltage signal;

a frequency divider connected to the voltage control oscillator to receive the voltage control oscillator signal, the frequency divider configured to generate a frequency divider output;

a phase-frequency detector connected to the frequency divider and configured to receive the frequency divider output and generate a phase-frequency detector output;

a charge pump connected to the phase-frequency detector and configured to receive the phase-frequency detector output and generate a charge pump output;

a multi-pole loop filter connected to the charge pump and the voltage control oscillator, the multi-pole loop filter configured to receive the charge pump output and generate the control voltage signal to the voltage control oscillator;

a receiver phase rotator circuit coupled to the receiver phase locked loop control circuit; and

a receiver phase buffer circuit connected to the receiver phase rotator circuit;

wherein the receiver phase rotator circuit is configured to acquire a clock phase from the receiver phase locked loop control circuit and modulo shift the clock phase into a desired phase angle.

4. The unified serial link system of claim 3 wherein the phase buffer circuit is a latch buffer configured with positive feedback through cross-coupled n-channels devices.

5. The unified serial link system of claim 3 wherein the phase buffer circuit comprises a pair of inverters.

6. The unified serial link system of claim 4 wherein the latch buffer comprises at least one CMOS, positive edge triggered latch circuit sampling latch.

7. A unified serial link system comprising a transmitter portion and a receiver portion, one of said transmitter portion and said receiver portion comprising a phase locked loop circuit control loop, the circuit control loop comprising:

a voltage control oscillator configured to generate a voltage control oscillator signal and a phase locked loop output signal responsive to a control voltage signal;

a frequency divider connected to the voltage control oscillator to receive the voltage control oscillator signal, the frequency divider configured to generate a frequency divider output;

a phase-frequency detector connected to the frequency divider and configured to receive the frequency divider output and generate a phase-frequency detector output;

a charge pump connected to the phase-frequency detector and configured to receive the phase-frequency detector output and generate a charge pump output; and

a multi-pole loop filter connected to the charge pump and the voltage control oscillator, the multi-pole filter comprising a ripple capacitor configured to attenuate charge pump ripple and a loop filter capacitor configured to stabilize the charge pump output and set a dominant pole, the multi-pole loop filter configured to receive the charge pump output and generate the control voltage signal to the voltage control oscillator.

8. The unified serial link system of claim 7, wherein the voltage control oscillator further comprises a plurality of tunable delay cells, said delay cells configured to have a tunable delay of from about 80 ps to about 125 ps.

9. A method for a unified serial link, comprising the steps of:

transmitting or receiving by phase locked loop steps, said phase locked loop steps comprising the steps of;

generating a voltage control oscillator signal and a phase locked loop output signal responsive to a control voltage signal and a coarse control voltage signal;

generating a frequency divider output responsive to the voltage control oscillator signal;

generating a phase-frequency detector output responsive to the frequency divider output;

generating a charge pump output responsive to the phase-frequency detector output;

generating the control voltage signal by filtering the charge pump output;

generating a voltage comparator output by comparing the control voltage signal and a reference signal;

generating a control logic output responsive to the comparator output;

converting the control logic output into a control voltage output; and

generating the coarse control voltage signal by filtering the control voltage output.

10. A method for a unified serial link, comprising the steps of transmitting by phase locked loop steps, said phase locked loop steps comprising the steps of:

generating a first voltage control oscillator signal and a phase locked loop output signal responsive to a control voltage signal;

generating a first frequency divider output responsive to the first voltage control oscillator signal;

generating a second frequency divider output from an LC signal;

generating a second phase-frequency detector output detector responsive to the second frequency divider output;

generating a second charge pump output responsive to the second phase-frequency detector output;

generating a second voltage signal by filtering the second charge pump output;

generating the LC signal responsive to the second voltage signal;

generating a first phase-frequency detector output responsive to the first frequency divider output and the second frequency divider output;

generating a first charge pump output responsive to the first phase-frequency detector output;

generating the first control voltage signal responsive to the first charge pump output;

re-powering the phase locked loop output signal; and

equalizing the re-powered phase locked loop output signal.

11. A method for a unified serial link, comprising the steps of:

receiving by phase locked loop steps, said phase locked loop steps comprising the steps of;

generating a voltage control oscillator signal and a phase locked loop output signal responsive to a control voltage signal;

generating a frequency divider output responsive to the voltage control oscillator signal;

generating a phase-frequency detector output responsive to the frequency divider output;

generating a charge pump output responsive to the phase-frequency detector output;

generating the control voltage signal responsive to the charge pump output;

acquiring a clock phase from the phase locked loop output signal;

modulo shifting the clock phase into a desired phase angle output; and

buffering the phase angle output.

12. The method of claim 11 wherein the step of buffering the phase angle output comprises using a latch buffer, further comprising the step of configuring the latch buffer with positive feedback through cross-coupled n-channel devices.

13. The method of claim 11 wherein the step of buffering the phase angle output comprises using a pair of inverters.

14. The method of claim 12 wherein the step of using a latch buffer comprises using at least one CMOS, positive edge triggered latch circuit sampling latch.

15. A method for a unified serial link, comprising the steps of:

transmitting or receiving by phase locked loop steps, said phase locked loop steps comprising the steps of;

generating a voltage control oscillator signal and a phase locked loop output signal responsive to a control voltage signal;

generating a frequency divider output responsive to the voltage control oscillator signal;

generating a phase-frequency detector output responsive to the frequency divider output;

generating a charge pump output responsive to the phase-frequency detector output;

generating the control voltage signal responsive to the charge pump output by attenuating charge pump ripple; and

stabilizing the charge pump output and setting a dominant pole.

16. The method of claim 15, wherein the step of generating the voltage control oscillator signal and the phase locked loop output signal comprises using a plurality of tunable delay cells, further comprising the step of tuning said delay cells to a delay of from about 80 ps to about 125 ps.