Low jitter digital frequency synthesizer and control thereof
First Claim
1. A method for controlling a low jitter digital frequency synthesizer, the method comprises:
- counting cycles of an input clock to produce an input clock count;
counting cycles of an output clock to produce an output clock count;
when the input clock count reaches a value of D, incrementing a first counter to produce an incremented first count;
when the output clock count reaches a value of M, incrementing a second counter to produce an incremented second count;
periodically taking a snapshot of the incremented first count to produce a snapshot first count;
periodically taking a snapshot of the incremented second count to produce a snapshot second count;
generating an error value based on the snapshot first count and the snapshot second count; and
adjusting a delay line tap value based on the error value.
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Abstract
A low jitter digital frequency synthesizer includes a first counter module, a second counter module, a snapshot module, an error value generation module, and a tapped delay line. The first counter module counts intervals of M cycles of an input clock to produce a first count. The second counter module count intervals of D cycles of an output clock to produce a second count, wherein a rate of the output clock corresponds to M/D times a rate of the input clock. The snapshot module periodically takes a snapshot of the first and second counts to produce snapshots. The error value generation module generates an error value based on the snapshots. The tapped delay line module produces the output clock based on the error value.
38 Citations
36 Claims
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1. A method for controlling a low jitter digital frequency synthesizer, the method comprises:
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counting cycles of an input clock to produce an input clock count; counting cycles of an output clock to produce an output clock count; when the input clock count reaches a value of D, incrementing a first counter to produce an incremented first count; when the output clock count reaches a value of M, incrementing a second counter to produce an incremented second count; periodically taking a snapshot of the incremented first count to produce a snapshot first count; periodically taking a snapshot of the incremented second count to produce a snapshot second count; generating an error value based on the snapshot first count and the snapshot second count; and adjusting a delay line tap value based on the error value. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. An apparatus for controlling a low jitter digital frequency synthesizer, the apparatus comprises:
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a processing module; and memory operably coupled to the processing module, wherein the memory stores operational instructions that cause the processing module to; count cycles of an input clock to produce an input clock count; count cycles of an output clock to produce an output clock count; when the input clock count reaches a value of D, increment a first counter to produce an incremented first count; when the output clock count reaches a value of M, increment a second counter to produce an incremented second count; periodically take a snapshot of the incremented first count to produce a snapshot first count; periodically take a snapshot of the incremented second count to produce a snapshot second count; generate an error value based on the snapshot first count and the snapshot second count; and adjust a delay line tap value based on the error value. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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19. A low jitter digital frequency synthesizer comprises:
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a first counter module operably coupled to count intervals of M cycles of an input clock of the low jitter digital frequency synthesizer to produce a first count; a second counter module operably coupled to count intervals of D cycles of an output clock of the low jitter digital frequency synthesizer to produce a second count, wherein a rate of the output clock corresponds to M/D times a rate of the input clock; a snapshot module operably coupled to periodically take a snapshot of the first count to produce a first snapshot and of the second count to produce a second snapshot; an error value generation module operably coupled to generate an error value based on the first and second snapshots; and a tapped delay line module operably coupled to produce the output clock based on the error value. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27)
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28. A programmable logic device comprises:
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a programmable logic fabric; memory operably coupled to the programmable logic fabric; an input/output section operably coupled to the programmable logic fabric and to the memory, wherein the input/output section includes a low jitter digital frequency synthesizer that includes; a first counter module operably coupled to count intervals of M cycles of an input clock of the low jitter digital frequency synthesizer to produce a first count; a second counter module operably coupled to count intervals of D cycles of an output clock of the low jitter digital frequency synthesizer to produce a second count, wherein a rate of the output clock corresponds to M/D times a rate of the input clock; a snapshot module operably coupled to periodically take a snapshot of the first count to produce a first snapshot and of the second count to produce a second snapshot; an error value generation module operably coupled to generate an error value based on the first and second snapshots; and a tapped delay line module operably coupled to produce the output clock based on the error value. - View Dependent Claims (29, 30, 31, 32, 33, 34, 35, 36)
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Specification