Method and system for monitoring a telecommunications signal transmission link

• US 7,143,197 B1
• Filed: 05/18/2000
• Issued: 11/28/2006
• Est. Priority Date: 11/08/1999
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Lloyd, Geoffrey D.
• Primary Examiner(s): Follansbee, John
• Assistant Examiner(s): SIDDIQI, MOHAMMAD A
• Application Number:
  US09/573,266
• Time in Patent Office: 2,385 Days
• Field of Search: 709/221, 709/222, 709/227, 709223-224, 709213-214, 709/250, 370/506, 370/509, 370/352, 370240-253, 370/230.1, 370/236, 340/9, 340/14, 340/452.2, 340/515, 710261-269, 714/1, 714/100
• US Class Current: 709/250
• CPC Class Codes: G06F 9/542 Event management; Broadcasting; Multicasting; Notifications
• CPC Class Codes: H04L 41/0604 using filtering, e.g. reduction of information by using priority, element types, position or time
• CPC Class Codes: H04L 41/064 involving time analysis
• CPC Class Codes: H04L 43/0811 by checking connectivity
• CPC Class Codes: H04L 43/16 Threshold monitoring

Abstract

A system including an event monitor monitoring at least one transmission link. Each event monitor receives transmission link addresses from an address sequencer and transmits related event data to a centralized storage register. The address sequencer also transmits the addresses to the storage register. The event monitor compares new event data for each address with old event data stored by the event monitor. If a difference is detected, the event monitor sends a strobe signal to the storage register, which stores the event data reflecting the difference and the related address data. The strobe signal is also sent to a signaling device, which sends an interrupt signal to cause a microprocessor to read the event and address data from the storage register. Optionally, the signaling device does not send an interrupt signal until a threshold number of strobe signals have been received.

Claims

1. A monitoring system for monitoring a plurality of signal-carrying transmission links for occurrence of an event, the system comprising:

an event monitor connected to a plurality of transmission links, each of said transmission links having a respective transmission link address, said event monitor repeatedly receiving data from each of the plurality of transmission links, said event monitor having a memory for storing data for each of the addresses and a comparator for comparing previously received data stored in the memory to presently received data for each of the addresses;

a storage register coupled to receive a datastream from said event monitor and to selectively store an event data portion of the datastream responsive to receipt of a predetermined signal;

an address sequencer for successively generating and transmitting to said storage register address data corresponding to the transmission link addresses;

said event monitor being connected to receive the address data from said address sequencer and responsively transmit to said storage register in the datastream data corresponding to each address, and to transmit said predetermined signal to said storage register when the comparator detects a difference between the previously received data stored in the memory and the presently received data for each of the addresses; and

a signaling device connected to receive the predetermined signal from said event monitor and transmit an interrupt signal to cause a microprocessor to read the event data from said storage register responsive thereto.

2. The monitoring system of claim 1, wherein said address data is transmitted from said address sequencer to said storage register in a datastream and wherein said storage register stores the event data received from said event monitor and the address data received from said address sequencer corresponding to the event data responsive to receipt of the predetermined signal.

3. The monitoring system of claim 2, wherein said storage register associates in memory event data received from said event monitor with address data received from said address sequencer simultaneously with receipt of the event data.

4. The monitoring system of claim 1, further comprising the microprocessor for reading said storage register responsive to receipt of the interrupt signal.

5. The monitoring system of claim 1, wherein said signaling device is configured to transmit the interrupt signal to the microprocessor upon receipt of the predetermined signal from said event monitor.

6. The monitoring system of claim 1, wherein said signaling device is configured to transmit the interrupt signal to said microprocessor after receipt of a predetermined number of said predetermined signals.

7. The monitoring system of claim 1, wherein said event monitor comprises a plurality of event monitors.

8. The monitoring system of claim 7, wherein each address identifies a port of the event monitor and a channel of the transmission link on which the event occurred.

9. The monitoring system of claim 8, wherein the event data comprises a first dataset indicating a message type and a second dataset comprising message data.

10. The monitoring system of claim 2, wherein said storage register comprises first and second storage fields and each of said storage fields is writeable to store a bit value which is changeable between a default value, indicating an absence of either event data or address data in the bit value'"'"'s respective storage field, and a flag value, indicating a presence of event data and address data in the bit value'"'"'s respective storage field.

11. An event monitor for monitoring a transmission link connectable thereto, the event monitor comprising:

means for receiving data from a transmission link;

means for receiving address data from an address sequencer, the address data corresponding to addresses of the transmission link;

means for storing data for each of the addresses;

means for transmitting the presently received data for each of the addresses to a storage register;

means for comparing previously stored data to presently received data for each of the addresses and for storing the presently received data for each of the addresses; and

means for transmitting a predetermined signal to the storage register to cause the storage register to store the particular address and a related event data portion of the presently received data if a difference is detected between the presently received data and the previously stored data for a particular address.

12. A monitoring system for monitoring a plurality of signal-carrying transmission link for occurrence of an event, the system comprising:

an event monitor connected to a plurality of transmission links having transmission link addresses, said event monitor receiving data from each of the plurality of transmission links and having a memory for storing data for each of the addresses and a comparator for comparing previously received data stored in the memory to presently received data for each of the addresses;

a storage register coupled to receive a datastream from said event monitor and store an event data portion of the datastream responsive to receipt of a predetermined signal;

an address sequencer for successively generating and transmitting to said storage register address data corresponding to the addresses;

said event monitor being connected to receive the address data from said address sequencer and responsively transmit to said storage register in a datastream the data corresponding to each address, and to transmit said predetermined signal to said storage register when the comparator detects a difference between the previously received data stored in the memory and the presently received data for each of the addresses;

a delay circuit connected to said event monitor for transmitting a trigger signal after expiration of a specified delay; and

a signaling device connected to receive the trigger signal from said delay circuit and transmit an interrupt signal to cause a microprocessor to read the event data from said storage register responsive thereto.

13. The monitoring system of claim 12, wherein said delay circuit comprises a timer and a logic circuit for determining whether the timer has expired.

14. The monitoring system of claim 13, further comprising a microprocessor for reading said storage register responsive to receipt of the interrupt signal and for resetting the timer of said delay circuit.