Methods and apparatus for backing up a memory device

• US 7,143,298 B2
• Filed: 04/18/2002
• Issued: 11/28/2006
• Est. Priority Date: 04/18/2002
• Status: Expired due to Fees

• Current Assignee: GE Fanuc Automation North America Incorporated
• Original Assignee: GE Fanuc Automation North America Incorporated
• Inventors: Wells, Owen Newton, Pfister, Todd Philip
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): Bae, Ji H.
• Application Number:
  US10/124,973
• Publication Number:
  US 20030200382A1
• Time in Patent Office: 1,685 Days
• Field of Search: 714/6, 711/106, 711/128, 365/63, 365/222, 361/15, 361/77
• US Class Current: 713/300
• CPC Class Codes: G06F 1/30 Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations for resetting only G06F1/24
• CPC Class Codes: G06F 11/1441 Resetting or repowering

Abstract

A memory module for a computer-based system. The memory module includes at least one memory device that requires periodic refresh signals to maintain data and is mounted on the memory module, and a circuit mounted on the memory module and configured to retain data stored on the memory device when the computer-based system loses power. In a separate embodiment, a control circuit is configured to logically detach at least one memory device from at least one memory controller when a computer-based system loses power, and retain data stored on the memory device when the computer-based system loses power.

Claims

1. A memory module for a computer-based system including a memory controller, said memory module comprising:

at least one memory device that requires periodic refresh signals to maintain data, said at least one memory device mounted on said memory module;

a circuit mounted on said memory module and configured to retain data stored on said memory device when the computer-based system loses power;

a comparator configured to determine whether a supply of power to the memory controller is less than a threshold, wherein said comparator is located on said memory module separate from the memory controller that refreshes said at least one memory device, wherein the memory controller refreshes said at least one memory device when the supply of power is greater than the threshold; and

a transistor coupled to said circuit and configured to maintain a line in a grounded state when the computer-based system loses power.

2. A memory module in accordance with claim 1, wherein said memory device comprises a synchronous dynamic random access memory (SDRAM) device.

3. A memory module in accordance with claim 1, wherein said memory device comprises a Rambus dynamic random access memory (RDRAM) device.

4. A memory module in accordance with claim 1, wherein said memory device comprises a double data rate synchronous dynamic random access memory (DDR SDRAM).

5. A memory module in accordance with claim 1, wherein said memory module comprises a dual in-line memory module (DIMM).

6. A memory module in accordance with claim 1, wherein said memory module comprises a small-outline dual in-line memory module (SO-DIMM).

7. A memory module in accordance with claim 1, wherein said circuit configured to maintain said memory device in a self refresh power down state, and wherein said memory device generates internal refresh signals to maintain data.

8. A memory module in accordance with claim 1, wherein said circuit configured to maintain said memory device in a self refresh power down state, and wherein said circuit generates internal refresh signals to maintain data.

9. A memory module in accordance with claim 1, wherein said circuit configured to signal said memory device to come out of a self refresh power down state, wherein at least one of said circuit and said memory device generates internal refresh signals to maintain data, said circuit configured to signal said memory device into a normal operating mode when said circuit senses the host memory controller is operating normally and issuing normal refresh signals.

10. A memory module in accordance with claim 1, wherein said circuit configured to, when signaled by the memory controller, signal said memory device into a self refresh power down state, and wherein said memory device generates internal refresh signals to maintain data.

11. A memory module in accordance with claim 1, wherein said circuit configured to, when signaled by the memory controller, signal said memory device into a self refresh power down state and wherein said circuit generates internal refresh signals to maintain data.

12. A memory module in accordance with claim 1, wherein said circuit configured to signal said memory device to come out of the self refresh power down state, and wherein at least one of said circuit and said memory device generates internal refresh signals to maintain data, said circuit configured to signal said memory device into a normal operating mode when the computer-based system is no longer in a reset state due to power loss or other causes.

13. A memory module in accordance with claim 1, wherein said circuit and said memory device configured to retain data stored on said memory device when the computer-based system loses power without receiving a refresh signal from the computer-based system.

14. A memory module in accordance with claim 5, wherein the computer-based system includes a motherboard having a DIMM slot, said DIMM is configured to be inserted within the DIMM slot.

15. A memory module in accordance with claim 6, wherein the computer-based system includes a motherboard having a SO-DIMM slot, said SO-DIMM is configured to be inserted within the SO-DIMM slot.

16. A memory module in accordance with claim 1, wherein said circuit comprises a serial presence detect (SPD) electrically-erasable programmable read-only memory (EEPROM).

17. A memory module in accordance with claim 1, wherein said circuit comprises a voltage regulator, a large-value super capacitor, and a battery, wherein said large-value super capacitor electrically connected in parallel with said battery between said battery and said voltage regulator.

20. A memory module in accordance with claim 17, wherein said large-value super capacitor is a 5.5 volt, 1.0 F capacitor.

21. A memory module in accordance with claim 17, wherein said battery is a 3 volt, 1000A-h lithium coin cell battery.

22. A memory module in accordance with claim 17, wherein said circuit further comprises a charge pump electrically coupled between a computer-based system power supply and said battery.

23. A memory module in accordance with claim 22, wherein said charge pump facilitates holding said large-value super capacitor charged.

24. A memory module in accordance with claim 22, wherein said charge pump is a 2.7–

5.5 volt input, 5 volt output regulated charge pump.

25. A memory module in accordance with claim 7, wherein said memory device generates the refresh signals using an internally generated clock and a refresh and word addressing counter.

26. A memory module in accordance with claim 8, wherein said circuit generates the refresh signals using an internally generated clock and a refresh and word addressing counter.

18. A memory module for a computer-based system, said memory module comprising:

at least one memory device that requires periodic refresh signals to maintain data, said at least one memory device mounted on said memory module;

a circuit mounted on said memory module and configured to retain data stored on said at least one memory device when the computer-based system loses power, wherein said circuit comprises a voltage regulator, a large-value super capacitor, and a battery, wherein said large-value super capacitor electrically connected in parallel with said battery between said battery and said voltage regulator, wherein said voltage regulator is a micropower single-ended primary inductance converter (SEPIC) voltage regulator; and

a transistor coupled to said circuit and configured to maintain a line in a grounded state when the computer-based system loses power.

19. A memory module in accordance with claim 18, wherein said voltage regulator regulates input voltages from 1.2 volts-15 volts to a 3.3 volt output.

27. A method for retaining data saved on a memory device in a computer-based system, the computer-based system including a power supply and a memory controller, at least one memory module having at least one memory device that requires periodic refresh signals to maintain data, and a circuit mounted on the memory module, said method comprising:

sensing an impending loss of power from the computer-based system power supply;

using the circuit, signaling the memory device into a self refresh power down state, wherein at least one of the memory device and the circuit generates internal refresh signals to maintain data;

using the circuit, maintaining the self refresh power down state while the computer-based system is inactive;

determining, by a comparator, whether a supply of power to the memory controller is less than a threshold, wherein the comparator is located on the memory module separate from the memory controller that refreshes the memory device, wherein the memory controller refreshes the memory device when the supply of power is greater than the threshold; and

maintaining a line coupled to the circuit in a grounded state when the computer-based system loses power.

28. A method in accordance with claim 27, wherein said sensing an impending loss of power from the computer-based system power supply comprises sensing an impending loss of power using the computer-based system.

29. A method in accordance with claim 27, wherein at least one of the memory device and the circuit include an internally generated clock and a refresh and word addressing counter, said method further comprising generating internal refresh signals using the internally generated clock and the refresh and word addressing counter.

30. A method in accordance with claim 27, further comprising:

sensing the host memory controller is operating normally and issuing normal refresh signals; and

using the circuit, signaling the memory device to come out of the self refresh power down state and into a normal operating mode.

33. A method in accordance with claim 27, wherein the memory device comprises a synchronous dynamic random access memory (SDRAM) device, said maintaining the self refresh power down state while the computer-based system is inactive comprising maintaining the SDRAM device in the self-refresh power down state using the circuit.

34. A method in accordance with claim 27, wherein the memory device comprises a Rambus dynamic random access memory (RDRAM) device, said maintaining the self refresh power down state while the computer-based system is inactive comprising maintaining the RDRAM device in the self-refresh power down state using the circuit.

35. A method in accordance with claim 27, wherein the memory device comprises a double data rate synchronous dynamic random access memory (DDR SDRAM) device, said maintaining the self refresh power down state while the computer-based system is inactive comprising maintaining the DDR SDRAM device in the self-refresh power down state using the circuit.

31. A method for retaining data saved on a memory device in a computer-based system, the computer-based system including a power supply, at least one memory module having at least one memory device that requires periodic refresh signals to maintain data, and a circuit mounted on the memory module, said method comprising:

sensing an impending loss of power from the computer-based system power supply;

using the circuit, signaling the memory device into a self refresh power down state, wherein at least one of the memory device and the circuit generates internal refresh signals to maintain data;

using the circuit, maintaining the self refresh power down state while the computer-based system is inactive, wherein the circuit includes a voltage regulator, a battery, and a large-value super capacitor electrically connected in parallel with the battery between the battery and the voltage regulator, said maintaining the self refresh power down state while the computer-based system is inactive comprising powering the memory device using the voltage regulator, the battery, and the large-value super capacitor;

and

maintaining a line coupled to the circuit in a grounded state when the computer-based system loses power.

32. A method in accordance with claim 31, wherein the circuit further comprises a charge pump electrically coupled between the computer-based system power supply and the battery, said maintaining the self refresh power down state while the computer-based system is inactive comprising facilitating holding the large-value super capacitor charged using the charge pump.

36. A control circuit for controlling at least one memory device in a computer-based system having at least one memory controller, said circuit comprising:

at least one memory device that requires periodic refresh signals to maintain data, said circuit configured to logically detach said at least one memory device from the at least one memory controller when the computer-based system loses power and retain data stored on said memory device when the computer-based system loses power;

a programmable logic device (PLD) configured to initiate a time count to a specific value upon receiving a signal from the computer-based system indicating to enter in a self-refresh mode, wherein a supply of power to the at least one memory controller is less than a threshold during the self-refresh mode, wherein said PLD is separate from said at least one memory device; and

a transistor configured to remove power from said PLD when the computer-based system loses power.

37. A control circuit in accordance with claim 36, wherein said control circuit configured to signal said at least one memory device into a self-refresh power down state, and wherein at least one of said memory device and said circuit generates internal refresh signals to maintain data when the computer-based system loses power.

38. A control circuit in accordance with claim 37, wherein the at least one memory controller does not support the power management memory functions used for signaling memory devices into the self refresh power down state.

39. A control circuit in accordance with claim 36, wherein said control circuit configured to maintain said memory device in a self-refresh power down state wherein at least one of said memory device and said circuit generates internal refresh signals to maintain data.

40. A control circuit in accordance with claim 37, wherein said control circuit configured to signal said memory device to come out of the self-refresh power down state and into a normal operating mode when the computer-based system is no longer in at least one of a reset state and a unstable state.

41. A control circuit in accordance with claim 36, wherein said circuit configured to retain data stored on said at least one memory device when the computer-based system loses power without receiving a refresh signal from the computer-based system.

42. A control circuit in accordance with claim 37, wherein at least one of said memory device and said circuit generates the refresh signals using an internally generated clock and a refresh and word addressing counter.

43. A control circuit in accordance with claim 36, wherein said circuit further comprises at least one multiplexer.

44. A control circuit in accordance with claim 43, wherein said multiplexer is a high-speed multiplexer.

45. A control circuit in accordance with claim 43, wherein said multiplexer configured to select control of said at least one memory device between said PLD and the at least one memory controller.

46. A control circuit in accordance with claim 36, wherein the at least one memory controller is embedded within a microprocessor.

47. A control circuit in accordance with claim 43, wherein said PLD logically detaches said at least one memory device from the at least one memory controller when the computer-based system loses power.

48. A control circuit in accordance with claim 43, wherein said PLD configured to command said at least one memory device into a self-refresh power-down mode, and wherein at least one of said circuit and said memory device generates a refresh signal for said at least one memory device.

49. A control circuit in accordance with claim 43, wherein the computer-based system includes a battery, said multiplexer and said PLD powered from the battery.

50. A control circuit in accordance with claim 43 wherein said PLD powers down when the computer-based system loses power.

51. A control circuit in accordance with claim 43, wherein said PLD powered off by a FET controlled by a computer-based system reset signal.

52. A control circuit in accordance with claim 36, wherein said memory device comprises a synchronous dynamic random access memory (SDRAM) device.

53. A control circuit in accordance with claim 36, wherein said memory device comprises a Rambus dynamic random access memory (RDRAM) device.

54. A control circuit in accordance with claim 36, wherein said memory device comprises a double data rate synchronous dynamic random access memory (DDR SDRAM) device.

55. A control circuit in accordance with claim 37, wherein said control circuit configured to signal said memory device to come out of the self-refresh power down state and into a normal operating mode when said circuit senses the memory controller is operating normally and issuing normal refresh signals.

56. A control circuit in accordance with claim 36, wherein said control circuit mounted to a detachable memory module.

57. A control circuit in accordance with claim 36, wherein the computer-based system includes a main circuit board, said control circuit mounted on the main circuit board.

58. A control circuit in accordance with claim 36, wherein the computer-based system includes a main circuit board and a separate circuit board, said control circuit mounted on the main circuit board.

63. A control circuit in accordance with claim 36, wherein said programmable logic device configured to finish the time count to the specific value before sending a signal to the at least one memory device indicating to enter the self-refresh mode.

64. A control circuit in accordance with claim 36, wherein said programmable logic device configured to discontinue the time count to the specific value upon receiving a signal that a power supply to the computer-based system has reached a specific level.

65. A control circuit in accordance with claim 36, wherein said at least one memory device cannot be accessed by the computer-based system during a refresh of said at least one memory device.

66. A control circuit in accordance with claim 36, wherein said at least one memory device enters the self-refresh mode upon receiving a command sequence including a precharge command, a no operation command, and a self-refresh command.

59. A method for retaining data saved on at least one memory device in a computer-based system using a circuit, the computer-based system including a power supply and a memory controller, the memory device requiring periodic refresh signals to maintain data, said method comprising:

sensing an impending loss of power from the computer-based system power supply;

logically detaching the memory device from the memory controller using the circuit;

initiating, by a programmable logic device, a time count to a specific value upon receiving a signal from the computer-based system indicating to enter in a self-refresh mode, wherein a supply of power to the memory controller is less than a threshold during the self-refresh mode, wherein the programmable logic device is separate from the at least one memory device.

60. A method in accordance with claim 59, wherein the memory device includes a self-refresh power-down state, wherein at least one of the circuit and the memory device generates a refresh signal for the at least one memory device, said logically detaching the memory device from the memory controller using the circuit comprises signaling the memory device into the self-refresh power-down state.

61. A method in accordance with claim 59, wherein the memory device comprises a synchronous dynamic random access memory (SDRAM) device, said logically detaching the memory device from the memory controller comprising logically detaching the SDRAM device from the memory controller.

62. A method in accordance with claim 59, wherein the memory device comprises a Rambus dynamic random access memory (RDRAM) device, said logically detaching the memory device from the memory controller comprising logically detaching the RDRAM device from the memory controller.