Resonance reduction arrangements

• US 7,143,381 B2
• Filed: 12/31/2002
• Issued: 11/28/2006
• Est. Priority Date: 12/31/2002
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Taylor, Greg, Zhao, Cangsang
• Primary Examiner(s): Kik, Phallaka
• Application Number:
  US10/331,649
• Publication Number:
  US 20040128625A1
• Time in Patent Office: 1,428 Days
• Field of Search: 716/4, 716/10, 326/33, 326/22, 326/28, 327/380, 327/381, 363/50, 323/312, 438/25, 438/26
• US Class Current: 716/133
• CPC Class Codes: G06F 30/36 Circuit design at the analogue level

Abstract

Resonance reduction arrangements to reduce the impact of power supply resonance on circuits, comprising a resonance sensor and a charge dumper, wherein upon the detection of the predetermined resonance by the resonance sensor at a circuit location, the charge dumper dumps charges at least one of from and to the circuit location, wherein the charge dumper comprises at least one gating transistor to dump the charges, the at least one gating transistor is directly connected to a first power supply line having a first potential and a second power supply line having a second potential of a different potential than the first potential.

Claims

1. A resonance reduction circuit comprising:

a resonance sensor to detect for predetermined resonance at a circuit location; and

a charge dumper to dump charges at least one of from and to the circuit location upon detection of the predetermined resonance by the resonance sensor, the charge dumper comprising at least one gating transistor to dump the charges, the at least one gating transistor directly connected to a first power supply line having a first potential and a second power supply line having a second potential of a different potential than the first potential.

2. A resonance reduction circuit as claimed in claim 1, wherein the resonance reduction circuit is an on-die integrated circuit (IC).

3. A resonance reduction circuit as claimed in claim 1, wherein the resonance reduction circuit is part of an integrated circuit (IC) package, and wherein the predetermined resonance pertains to a predetermined IC package resonance.

4. A resonance reduction circuit as claimed in claim 1, wherein the resonance sensor is a power grid resonance sensor to detect for predetermined resonance of a power grid.

5. An integrated circuit (IC) comprising:

a resonance reduction circuit including;

a resonance sensor to detect for predetermined resonance at a circuit location; and

a charge dumper to dump charges at least one of from and to the circuit location upon detection of the predetermined resonance by the resonance sensor, the charge dumper comprising at least one gating transistor to dump the charges, the at least one gating transistor directly connected to a first power supply line having a first potential and a second power supply line having a second potential of a different potential than the first potential.

6. An IC as claimed in claim 5, wherein the resonance reduction circuit is part of a monolithic on-die circuit.

7. An IC as claimed in claim 5, wherein the resonance reduction circuit is an IC on an IC package, and wherein the predetermined resonance pertains to a predetermined IC package resonance.

8. An IC as claimed in claim 5, wherein the resonance sensor is a power grid resonance sensor to detect for predetermined resonance of a power grid.

9. An electronic package comprising:

a die; and

a resonance reduction circuit including;

a resonance sensor to detect for predetermined resonance at a circuit location of the electronic package; and

a charge dumper to dump charges at least one of from and to the circuit location upon detection of the predetermined resonance by the resonance sensor, the charge dumper comprising at least one gating transistor to dump the charges, the at least one gating transistor directly connected to a first power supply line having a first potential and a second power supply line having a second potential of a different potential than the first potential.

10. An electronic package as claimed in claim 9, wherein the resonance reduction circuit is an on-die circuit.

11. An electronic package as claimed in claim 9, wherein the resonance reduction circuit is part of an IC on the electronic package, and wherein the predetermined resonance pertains to a predetermined electronic package resonance.

12. An electronic package as claimed in claim 9, wherein the resonance sensor is a power grid resonance sensor to detect for predetermined resonance of a power grid.

13. A system comprising:

at least one item selected from a list of;

an electronic package, PCB, socket, bus portion, input device, output device, power supply arrangement and case; and

a resonance reduction circuit including;

a resonance sensor to detect for predetermined resonance at a circuit location; and

a charge dumper to dump charges at least one of from and to the circuit location upon detection of the predetermined resonance by the resonance sensor, the charge dumper comprising at least one gating transistor to dump the charges, the at least one gating transistor directly connected to a first power supply line having a first potential and a second power supply line having a second potential of a different potential than the first potential.

14. A system as claimed in claim 13, wherein the resonance reduction circuit is an on-die circuit.

15. A system as claimed in claim 13, wherein the resonance reduction circuit is part of an IC of an electronic package, and wherein the predetermined resonance pertains to a predetermined electronic package resonance.

16. A system as claimed in claim 13, wherein the resonance sensor is a power grid resonance sensor to detect for predetermined resonance of a power grid.

17. A resonance reduction method comprising:

detecting for predetermined resonance at a circuit location; and

dumping charges at least one of from and to the circuit location upon detection of the predetermined resonance by using at least one gating transistor, the at least one gating transistor directly connected to a first power supply line having a first potential and a second power supply line having a second potential of a different potential than the first potential.

18. A resonance reduction method as claimed in claim 17, wherein the resonance reduction method is implemented by an on-die integrated circuit (IC).

19. A resonance reduction method as claimed in claim 17, wherein the resonance reduction method is implemented by part of an integrated circuit (IC) package, and wherein the predetermined resonance pertains to a predetermined IC package resonance.

20. A resonance reduction method as claimed in claim 17, wherein the detecting detects for predetermined resonance of a power grid, and wherein the dumping uses at least one gating transistor to dump the charges between a first power grid connection and a second power grid connection of a differing potential than the first power grid connection.

21. A method for reducing resonance comprising:

sensing resonance;

providing a signal to a charge dissipation stage when resonance is sensed;

recognizing the signal; and

dissipating charges from a first potential to a second potential where the second potential is lower than the first potential with at least one gating transistor, the at least one gating transistor directly connected to a first power supply line having a first potential and a second power supply line having a second potential of a different potential than the first potential.

22. A mounted electrical component arrangement comprising:

a plurality of electrical components; and

a circuit to reduce power supply package resonance mounted to a substrate within at least one of the electrical components, with the circuit including a sensing stage to detect resonance and a current dissipation stage to dump charges from a first potential to a second potential where the second potential is lower than the first potential, the current dissipation stage comprising at least one gating transistor to dump the charges, the at least one gating transistor directly connected to a first power supply line having a first potential and a second power supply line having a second potential of a different potential than the first potential.