Methods for producing packaged integrated circuit devices and packaged integrated circuit devices produced

• US 7,144,745 B2
• Filed: 08/07/2001
• Issued: 12/05/2006
• Est. Priority Date: 12/10/1999
• Status: Expired due to Term

• Current Assignee: Invensas Corporation
• Original Assignee: Tessera Technologies Hungary Kft. (Adeia Inc.)
• Inventors: Badehi, Avner Pierre
• Primary Examiner(s): Blum, David S.
• Application Number:
  US09/922,770
• Publication Number:
  US 20020027296A1
• Time in Patent Office: 1,946 Days
• Field of Search: 438/7, 438/51, 438/116
• US Class Current: 438/7
• CPC Class Codes: B81B 2207/097 Interconnects arranged on the substrate or the lid, and covered by the package seal
• CPC Class Codes: B81B 7/0067 for controlling the passage of optical signals through the package
• CPC Class Codes: B81B 7/007 Interconnections between the MEMS and external electrical signals
• CPC Class Codes: B81B 7/0077 Other packages not provided for in groups B81B7/0035 - B81B7/0074
• CPC Class Codes: B81C 1/00301 Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
• CPC Class Codes: B81C 2203/0118 Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
• CPC Class Codes: B81C 2203/032 Gluing
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/10 characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/14683 Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof not peculiar thereto H01L21/00
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/16235 Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
• CPC Class Codes: H03H 9/105 the enclosure being defined by a cover cap mounted on an element forming part of the BAW device
• CPC Class Codes: H03H 9/1057 for microelectro-mechanical devices
• CPC Class Codes: H03H 9/1092 the enclosure being defined by a cover cap mounted on an element forming part of the surface acoustic wave [SAW] device on the side of the IDT's

Abstract

A method of producing a crystalline substrate based device includes forming a microstructure on a crystalline substrate. At least one packaging layer is sealed over the microstructure by an adhesive and defines therewith at least one gap between the crystalline substrate and the at least one packaging layer.

Claims

1. A method of producing a crystalline substrate based device comprising:

providing a wafer including a semiconductor substrate and comprising a plurality of semiconductor microstructures each including at least one optoelectronic device;

providing a wafer-level transparent packaging layer;

forming a wafer-level spacer onto said wafer-level transparent packaging layer, said packaging layer and said spacer defining a plurality of cavities extending entirely through said spacer, the step of forming the wafer-level spacer including applying a spacer material separate from the wafer-level transparent packaging layer to the wafer-level transparent packaging layer;

then

sealing said wafer-level spacer to said wafer so that the cavities in the wafer-level spacer extend between the wafer and the transparent packaging layer; and

subsequently dicing said semiconductor substrate, having said wafer-level spacer and said wafer-level transparent packaging layer sealed thereunto, to form individual chip scale packaged devices each including a microstructure, a chip scale portion of said transparent packaging layer, and a cavity disposed between the microstructure and the portion of the transparent packaging layer,

wherein the process is performed without removing material of the wafer-level transparent packaging layer prior to said dicing step.

2. A method of producing a crystalline substrate based device according to claim 1 and wherein said sealing comprises using epoxy to seal said wafer-level spacer onto said wafer.

3. A method of producing a crystalline substrate based device according to claim 1 and wherein said semiconductor substrate comprises silicon.

4. A method of producing a crystalline substrate based device according to claim 1 and wherein said sealing comprises using an adhesive separate from said wafer-level spacer to seal said wafer-level spacer onto said semiconductor substrate.

5. A method of producing a crystalline substrate based device according to claim 4 and wherein said adhesive comprises epoxy.

6. A method for producing a crystalline substrate based device according to claim 1 and wherein said semiconductor substrate comprises silicon.

7. A method of producing a crystalline substrate based device according to claim 1 further comprising the step of forming electrical contacts prior to completion of the dicing step so that the contacts extend away from the wafer scale transparent packaging layer and so that after completion of the dicing step the contacts extend along edge surfaces of the individual chip scale packaged devices.

8. A method according to claim 7 wherein said dicing step includes forming channels extending through said crystalline substrate.

9. A method according to claim 8 further comprising the steps of depositing a layer material in said channels, said step of forming contacts being performed so that said contacts extend on said layer material.

10. A method according to claim 9 further comprising the step of forming notches in said layer material within said channels so that surfaces of said layer material in said notches will constitute edge surfaces of the individual chip scale packaged devices upon completion of the dicing step, the step of forming the contacts including forming the contacts on surfaces of the layer material in the notches.

11. A method according to claim 10 further comprising the step of bonding an underlying packaging layer to a rear surface of the crystalline substrate facing away from said transparent packaging layer.

12. A method according to claim 9 wherein said layer material is an epoxy.

13. A method of producing a crystalline substrate based device according to claim 1 wherein said step of forming the wafer level spacer includes applying a layer of the spacer material and selectively exposing the layer of spacer material to illumination so as to form the spacer from the layer of spacer material in a pattern defined by the selective illumination.

14. A method according to claim 13 wherein said spacer material is an epoxy photoresist.

15. A method according to claim 1 wherein said step of forming said wafer-level spacer includes forming the wafer-level spacer as an array of separate spacer elements on said wafer-level transparent packaging element.

16. A method according to claim 15 wherein said array of spacer elements includes pairs of spacer elements extending next to one another but separated from one another to define openings between them, wherein the sealing step is performed so as to position the spacer elements of each pair on mutually-adjacent ones of the microstructures in the wafer, and wherein the dicing step is performed so that the transparent wafer-level packaging element is cut in alignment with the openings.

17. A method according to claim16, wherein the sealing step includes applying an adhesive so that the adhesive extends into the openings, and wherein the dicing step includes dicing the adhesive in the openings.

18. A method according to claim 1 wherein each said optoelectronic device includes an array of microlenses, and wherein the sealing step is performed so that each array of microlenses is disposed within one of the cavities in the wafer-level spacer.

19. A method of making a plurality of chip scale packages comprising:

(a) uniting a unitary semiconductor wafer including a plurality of chips, a wafer level protective layer and a plurality of spacer elements so that the spacer elements are disposed between the wafer level protective layer and the wafer, so that each spacer element is disposed on one chip and defines a cavity between that chip and the wafer level protective layer, and so that there are openings between spacer elements disposed on adjacent chips, the uniting step including connecting the spacer elements to the wafer using an adhesive so that the adhesive extends into the openings; and

then

(b) dicing the wafer and wafer level protective layer along severance planes aligned with the openings and extending through the adhesive.

20. A method as claimed in claim 19 wherein said uniting step includes providing the spacer elements and the wafer level protective layer as a unit and assembling the unit with the wafer.

21. A method as claimed in claim 19 wherein the spacer elements are rectangular.

22. A method of making a chip scale package comprising:

(a) forming a wafer level spacer on a wafer level protective layer by applying a layer of a spacer material onto the wafer level protective layer, selectively exposing the layer of spacer material to illumination so as to form the spacer from the layer of spacer material in a pattern defined by the selective illumination; and

then

(b) assembling the wafer level protective layer and wafer level spacer with a semiconductor wafer including a plurality of chips and bonding the wafer level spacer to the semiconductor wafer; and

then

(c) dicing the wafer and wafer level protective layer.

23. A method according to claim 22 wherein said spacer material is an epoxy photoresist.

24. A method according to claim 22 wherein the step of bonding the wafer level spacer to the wafer includes providing an adhesive separate from the wafer level spacer between the wafer level spacer and the semiconductor wafer.

25. A method of producing a crystalline substrate based device comprising:

providing a wafer including a semiconductor substrate and comprising a plurality of semiconductor microstructures each including at least one optoelectronic image sensor;

providing a wafer-level transparent packaging layer;

forming a wafer-level spacer onto said wafer-level transparent packaging layer, said packaging layer and said spacer defining a plurality of cavities extending entirely through said spacer, the step of forming the wafer-level spacer including applying a spacer material separate from the wafer-level transparent packaging layer to the wafer-level transparent packaging layer;

then

sealing said wafer-level spacer to said wafer so that the cavities in the wafer-level spacer extend between the wafer and the transparent packaging layer; and

subsequently dicing said semiconductor substrate, having said wafer-level spacer and said wafer-level transparent packaging layer sealed thereunto, to form individual chip scale packaged devices each including a microstructure, a chip scale portion of said transparent packaging layer, and a cavity disposed between the microstructure and the portion of the transparent packaging layer,

wherein the process is performed without removing material from portions of the wafer-level transparent packaging layer overlying the image sensor prior to said dicing step.

26. A method of producing a crystalline substrate based device according to claim 25 and wherein said sealing comprises using epoxy to seal said wafer-level spacer onto said wafer.

27. A method of producing a crystalline substrate based device according to claim 25 and wherein said semiconductor substrate comprises silicon.

28. A method of producing a crystalline substrate based device according to claim 25 and wherein said sealing comprises using an adhesive separate from said wafer-level spacer to seal said wafer-level spacer onto said semiconductor substrate.

29. A method of producing a crystalline substrate based device according to claim 28 and wherein said adhesive comprises epoxy.

30. A method for producing a crystalline substrate based device according to claim 25 and wherein said semiconductor substrate comprises silicon.

31. A method of producing a crystalline substrate based device according to claim 25 further comprising the step of forming electrical contacts prior to completion of the dicing step so that the contacts extend away from the wafer scale transparent packaging layer and so that after completion of the dicing step the contacts extend along edge surfaces of the individual chip scale packaged devices.

32. A method according to claim 31 wherein said dicing step includes forming channels extending through said crystalline substrate.

33. A method according to claim 32 further comprising the steps of depositing a layer material in said channels, said step of forming contacts being performed so that said contacts extend on said layer material.

34. A method according to claim 33 further comprising the step of forming notches in said layer material within said channels so that surfaces of said layer material in said notches will constitute edge surfaces of the individual chip scale packaged devices upon completion of the dicing step, the step of forming the contacts including forming the contacts on surfaces of the layer material in the notches.

35. A method according to claim 34 further comprising the step of bonding an underlying packaging layer to a rear surface of the crystalline substrate facing away from said transparent packaging layer.

36. A method according to claim 34 wherein said layer material is an epoxy.

37. A method of producing a crystalline substrate based device according to claim 25 wherein said step of forming the wafer level spacer includes applying a layer of the spacer material and selectively exposing the layer of spacer material to illumination so as to form the spacer from the layer of spacer material in a pattern defined by the selective illumination.

38. A method according to claim 37 wherein said spacer material is an epoxy photoresist.

39. A method according to claim 25 wherein said step of forming said wafer-level spacer includes forming the wafer-level spacer as an array of separate spacer elements on said wafer-level transparent packaging element.

40. A method according to claim 39 wherein said array of spacer elements includes pairs of spacer elements extending next to one another but separated from one another to define openings between them, wherein the sealing step is performed so as to position the spacer elements of each pair on mutually-adjacent ones of the microstructures in the wafer, and wherein the dicing step is performed so that the transparent wafer-level packaging element is cut in alignment with the openings.

41. A method according to claim 40 wherein the sealing step includes applying an adhesive so that the adhesive extends into the openings, and wherein the dicing step includes dicing the adhesive in the openings.

42. A method according to claim 25 wherein each said optoelectronic image sensor includes an array of microlenses, and wherein the sealing step is performed so that each array of microlenses is disposed within one of the cavities in the wafer-level spacer.