Structure and material for assembling a low-K Si die to achieve a low warpage and industrial grade reliability flip chip package with organic substrate

• US 7,144,756 B1
• Filed: 05/10/2005
• Issued: 12/05/2006
• Est. Priority Date: 11/20/2003
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Wang, Wen-Chou Vincent, Li, Yuan, Fritz, Donald S.
• Primary Examiner(s): Lebentritt, Michael
• Assistant Examiner(s): Stevenson, Andre′
• Application Number:
  US11/126,571
• Time in Patent Office: 574 Days
• Field of Search: 438/6, 438/10, 438106-114, 438/104, 438/118, 438121-123, 438128-129, 438/135, 438/142, 438/145, 438/149, 438/151, 438/157, 438/176, 438/478, 438/184, 438/193, 438195-198, 438200-207, 438209-211, 438/218, 438/237, 438/165, 438/248, 438/168, 438/343, 438/294, 438/308
• US Class Current: 438/106
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 23/055 the leads having a passage through the base H01L23/057 takes precedence
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/0102 Calcium [Ca]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16195 Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/3511 Warping

Abstract

Provided are a semiconductor low-K Si die flip chip package with warpage control and fabrication methods for such packages. The packages include heat spreaders that are attached to the low-K Si die and packaging substrate. In general, the modulus of the thermal interface material, which is used to attach the heat spreader to the low-K Si die, is selected as high as possible relative to other commercially available thermal interface materials. On the other hand, the modulus of the adhesive, which is used to attach the heat spreader via an optional stiffener to the substrate, is selected as low as possible relative to other commercially available adhesives. The result is a package with less bowing and so improved co-planarity (in compliance with industry specifications) with the surface to which it is ultimately bound. Moreover, the low-K Si die and package reliabilities are thereby enhanced.

Claims

1. A method of forming a semiconductor package comprising:

providing a low-K Si die having front and back surfaces and a packaging substrate having die and board surfaces, the low-K Si die including a plurality of layers of low-K material;

connecting a heat spreader to the back surface of the low-K Si die with a thermal interface material having a modulus that is higher than or equal to 100 MPa; and

connecting the heat spreader to the die surface of the packaging substrate with an adhesive having a modulus that is lower than or equal to 10 MPa.

2. A method of forming a semiconductor package as recited in claim 1, further comprising:

cycling the temperature of the semiconductor package from −

55°

C. to 125°

C. to create internal stress within the semiconductor package, wherein the low-K Si die is stably integrated within the semiconductor package such that the reliability of the low-K Si die is not substantially impaired by the internal stress of the semiconductor package.

3. A method of forming a semiconductor package as recited in claim 1, wherein the low-K Si die is an extra low-K Si die including a plurality of layers of extra low-K material.

4. A method of forming a semiconductor package as recited in claim 1, wherein the layer of low-K material has a thickness of 6 microns or less.

5. A method of forming a semiconductor package as recited in claim 1, wherein the low-K Si die has a thickness in the range of 19 mil to 28 mil.

6. A method of forming a semiconductor package as recited in claim 1, wherein the low-K Si die size ranges from 2 mm×

2 mm to 30 mm×

30 mm.

7. A method of forming a semiconductor package as recited in claim 1, wherein the packaging substrate size ranges up to 45 mm×

45 mm.

8. A method of forming a semiconductor package as recited in claim 1, wherein the thermal interface material is has a modulus about 400 MPa.

9. A method of forming a semiconductor package as recited in claim 1, wherein the adhesive has a modulus about 4 MPa.

10. A method of forming a semiconductor package as recited in claim 1, further comprising:

electrically and mechanically coupling the front surface of the low-K Si die with the die surface of the packaging substrate.

11. A method of forming a semiconductor package as recited in claim 10, wherein the low-K Si die includes a plurality of solder bumps on the front surface of the low-K Si die for electrically and mechanically coupling the front surface of the low-K Si die with the die surface of the packaging substrate.

12. A method of forming a semiconductor package as recited in claim 11, wherein the plurality of solder bumps offset the low-K Si die from the packaging substrate such that a gap is formed in between the front surface of the low-K Si die and the die surface of the packaging substrate.

13. A method of forming a semiconductor package as recited in claim 12, further comprising:

filling in the gap with an underfill material.