Method of fabricating semiconductor components through implantation and diffusion in a semiconductor substrate

• US 7,144,796 B2
• Filed: 09/20/2004
• Issued: 12/05/2006
• Est. Priority Date: 09/19/2003
• Status: Active Grant

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Germany GmbH (Microchip Technology Incorporated)
• Inventors: Graf, Michael, Dietz, Franz, Dudek, Volker
• Primary Examiner(s): NGUYEN, THANH T
• Application Number:
  US10/946,506
• Publication Number:
  US 20050095804A1
• Time in Patent Office: 806 Days
• Field of Search: 438/545, 438223-224, 438227-228, 438/527, 257/335
• US Class Current: 438/545
• CPC Class Codes: H01L 21/2253 by ion implantation
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/76237 introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 29/1045 the doping structure being parallel to the channel length, e.g. DMOS like
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A semiconductor element such as a DMOS-transistor is fabricated in a semiconductor substrate. Wells of opposite conductivity are formed by implanting and then thermally diffusing respective well dopants into preferably spaced-apart areas in the substrate. At least one trench and active regions are formed in the substrate. The trench may be a shallow drift zone trench of a DMOS-transistor, and/or a deep isolation trench. The thermal diffusion of the well dopants includes at least one first diffusion step during a first high temperature drive before forming the trench, and at least one second diffusion step during a second high temperature drive after forming the trench. Dividing the thermal diffusion steps before and after the trench formation achieves an advantageous balance between reducing or avoiding lateral overlapping diffusion of neighboring wells and reducing or avoiding thermally induced defects along the trench boundaries.

Claims

1. A method of producing a semiconductor component in a semiconductor substrate, comprising steps:

a) forming a first well region having a first conductivity type and forming a second well region having a second conductivity type opposite said first conductivity type respectively in said semiconductor substrate;

b) forming at least one trench in said semiconductor substrate; and

c) forming and electrically contacting active regions in said semiconductor substrate;

wherein said forming of said first and second well regions in said step a) comprises steps;

a1) implanting a first well dopant into a first portion of said first well region and implanting a second well dopant into a second portion of said second well region;

a2) diffusing said first well dopant from said first portion partially farther into said first well region and diffusing said second well dopant from said second portion partially farther into said second well region by at least one first drive-in diffusion in a first high temperature drive step carried out before said forming of said at least one trench in said step b); and

a3) diffusing said first well dopant farther into said first well region and diffusing said second well dopant farther into said second well region by at least one second drive-in diffusion in a second high temperature drive step carried out after said forming of said at least one trench in said step b).

2. The method according to claim 1, further comprising carrying out said implanting of said first well dopant and said implanting of said second well dopant so that said first portion of said first well region and said second portion of said second well region are spaced apart from one another by a lateral spacing distance therebetween.

3. The method according to claim 2, further comprising selecting said lateral spacing distance and selecting a temperature and a duration of said first high temperature drive step and said second high temperature drive step so that a region free of said first and second well dopants implanted in said step a1) remains laterally between said first and second well regions in said semiconductor substrate after completion of said steps a2) and a3).

4. The method according to claim 1, wherein said step a3) diffuses said first well dopant entirely to a first well depth of and throughout a first well volume of said first well region and diffuses said second well dopant entirely to a second well depth of and throughout a second well volume of said second well region.

5. The method according to claim 4, wherein said step a2) diffuses said first well dopant to a first penetration depth in a range from 25% to 75% of said first well depth in said first well region and diffuses said second well dopant to a second penetration depth in a range from 25% to 75% of said second well depth in said second well region.

6. The method according to claim 5, wherein said first penetration depth is in a range from 40% to 60% of said first well depth and said second penetration depth is in a range from 40% to 60% of said second well depth.

7. The method according to claim 4, wherein said semiconductor substrate is disposed on an insulating layer, and said first and second well depths correspond to a total thickness of said semiconductor substrate so that said first and second well regions extend through said total thickness of said semiconductor substrate to said insulating layer.

8. The method according to claim 7, wherein said forming of said at least one trench includes forming a deep trench extending through said total thickness of said semiconductor substrate to said insulating layer.

9. The method according to claim 1, wherein said forming of said at least one trench includes forming a deep trench extending deeper than said first and second well regions into said semiconductor substrate.

10. The method according to claim 1, wherein said forming of said at least one trench includes forming a trench at a location that is not between said first and second well regions of said semiconductor component.

11. The method according to claim 1, wherein said forming of said at least one trench includes forming deep trenches laterally surrounding in said semiconductor substrate an isolated component box in which said first and second well regions and said active regions have been and/or will be formed.

12. The method according to claim 11, wherein said semiconductor substrate is disposed on an insulating layer, and wherein said deep trenches are formed to extend entirely through a thickness of said semiconductor substrate to said insulating layer.

13. The method according to claim 1, wherein said forming of said at least one trench includes forming a trench at a location between said first and second well regions.

14. The method according to claim 1, wherein said semiconductor component is a DMOS-transistor, wherein said forming of said at least one trench includes forming a shallow trench, and further comprising defining a drift zone of said DMOS-transistor along boundaries of said shallow trench.

15. The method according to claim 14, wherein said forming of said shallow trench comprises carrying out an STI process to produce said shallow trench.

16. The method according to claim 14, wherein said boundaries of said shallow trench include sidewalls and a floor, and wherein said defining of said drift zone comprises an additional process of separately doping said drift zone along said sidewalls and/or said floor of said shallow trench with at least one drift zone dopant.

17. The method according to claim 16, wherein said additional process of separately doping said sidewalls and/or said floor comprises implanting said at least one drift zone dopant into said sidewalls and/or said floor before said step a3) and then diffusing said at least one drift zone dopant into said drift zone along said sidewalls and/or said floor during said second high temperature drive step in said step a3).

18. The method according to claim 1, further comprising an additional step of forming in said semiconductor substrate a shallow trench distinct from said at least one trench before said step a2) and before said step b), and wherein said forming of said at least one trench in said step b) comprises forming a deep trench between said steps a2) and a3).

19. The method according to claim 18, further comprising implanting a drift zone dopant into at least one sidewall and/or a floor of said shallow trench before said step a3) and diffusing said drift zone dopant during said second high temperature drive step in said step a3).

20. The method according to claim 18, further comprising implanting a drift zone dopant into a drift zone location in said semiconductor substrate before said forming of said shallow trench, wherein said forming of said shallow trench is carried out to retain some of said drift zone dopant along at least one sidewall and/or a floor of said shallow trench, and further comprising diffusing said drift zone dopant during at least said second high temperature drive step in said step a3).

21. The method according to claim 1, wherein said forming of said at least one trench in said step b) comprises forming a shallow trench and a deep trench between said steps a2) and a3).

22. The method according to claim 21, further comprising implanting a drift zone dopant into a drift zone location in said semiconductor substrate before said forming of said shallow trench, wherein said forming of said shallow trench is carried out to retain some of said drift zone dopant along at least one sidewall and/or a floor of said shallow trench, and further comprising diffusing said drift zone dopant during at least said second high temperature drive step in said step a3).

23. The method according to claim 1, further comprising filling said at least one trench with a dielectric material.

24. The method according to claim 23, wherein said semiconductor substrate comprises a semiconducting material, and further comprising selecting said dielectric material from a group consisting of an oxide of said semiconducting material, a nitride of said semiconducting material, a polycrystalline material comprising at least one compositional component of said semiconducting material, and a multi-layer system comprising one or more of said oxide, said nitride and said polycrystalline material.

25. The method according to claim 1, further comprising coating a boundary surface of said at least one trench with a liner oxide after said step b) and before said step a3).