Semiconductor device and method of manufacturing the same
First Claim
1. A semiconductor device comprising:
- a semiconductor substrate;
a trench formed in the semiconductor substrate;
an island-like element region formed in the semiconductor substrate, having an upper surface, a first side surface exposed by the trench, a second side surface, and a third side surface opposing the second side surface, and having an upper portion including the upper surface, a middle portion positioned below the upper portion, and a lower portion positioned below the middle portion;
a gate insulating film formed on the first to third side surfaces in the upper portion of the element region;
a gate electrode having a portion extending over the upper surface of the element region and the second and third side surfaces in the upper portion of the element region, and having a first bottom surface positioned above the upper surface of the element region, and a second bottom surface positioned below the upper surface of the element region;
a first diffusion layer formed along the upper surface of the element region;
a second diffusion layer formed along the first side surface in the middle portion of the element region;
a channel region having a first region formed along the first side surface in the upper portion of the element region, a second region formed along the second side surface in the upper portion of the element region, and a third region formed along the third side surface in the upper portion of the element region;
a capacitor formed in the trench and adjacent to the lower portion of the element region; and
a bit line electrically connected to the first diffusion layer.
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Accused Products
Abstract
A semiconductor device includes a semiconductor substrate, a trench formed in the semiconductor substrate, an island-like element region formed in the semiconductor substrate, having an upper surface, first to third side surfaces, an upper portion, a middle portion and a lower portion, a gate insulating film formed on the first to third side surfaces in the upper portion of the element region, a gate electrode having first and second bottom surfaces, a first diffusion layer formed along the upper surface of the element region, a second diffusion layer formed along the first side surface in the middle portion of the element region, a channel region having first to third regions formed along the first to third side surfaces in the upper portion of the element region, a capacitor formed in the trench, and a bit line electrically connected to the first diffusion layer.
7 Citations
13 Claims
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1. A semiconductor device comprising:
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a semiconductor substrate; a trench formed in the semiconductor substrate; an island-like element region formed in the semiconductor substrate, having an upper surface, a first side surface exposed by the trench, a second side surface, and a third side surface opposing the second side surface, and having an upper portion including the upper surface, a middle portion positioned below the upper portion, and a lower portion positioned below the middle portion; a gate insulating film formed on the first to third side surfaces in the upper portion of the element region; a gate electrode having a portion extending over the upper surface of the element region and the second and third side surfaces in the upper portion of the element region, and having a first bottom surface positioned above the upper surface of the element region, and a second bottom surface positioned below the upper surface of the element region; a first diffusion layer formed along the upper surface of the element region; a second diffusion layer formed along the first side surface in the middle portion of the element region; a channel region having a first region formed along the first side surface in the upper portion of the element region, a second region formed along the second side surface in the upper portion of the element region, and a third region formed along the third side surface in the upper portion of the element region; a capacitor formed in the trench and adjacent to the lower portion of the element region; and a bit line electrically connected to the first diffusion layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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Specification