Circuits for transistor testing

• US 7,145,356 B2
• Filed: 12/23/2004
• Issued: 12/05/2006
• Est. Priority Date: 12/24/2003
• Status: Expired due to Fees

• Current Assignee: DONGBU ELECTRONICS CO., LTD. (DB HiTek Co., Ltd.)
• Original Assignee: DONGBU ELECTRONICS CO., LTD. (DB HiTek Co., Ltd.)
• Inventors: Sang Gi, Lee
• Primary Examiner(s): Nguyen, Vinh
• Assistant Examiner(s): Chan, Emily Y
• Application Number:
  US11/021,451
• Publication Number:
  US 20050156605A1
• Time in Patent Office: 712 Days
• Field of Search: 324/769, 324/158.1, 324750-765
• US Class Current: 324/762.09
• CPC Class Codes: G11C 2029/5002 Characteristic
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633

Abstract

Disclosed is a circuit for transistor testing, by which electrical stresses of separate conditions can be simultaneously applied to a plurality of transistors, respectively. According to one example, such a circuit may include a plurality of contact pads connectable to a plurality of terminals of a plurality of transistors, a plurality of first resistors connected to a plurality of gates of a plurality of the transistors, respectively by voltage distribution according to a resistance ratio, respectively, and a plurality of second resistors connected between a plurality of gate electrodes and drains of a plurality of the transistors, respectively wherein a plurality of voltages applied to a plurality of the gates of a plurality of the transistors are dropped by a plurality of the second resistors to be applied to a plurality of drains of a plurality of the transistors, respectively.

Claims

1. A circuit for testing a plurality of transistors including a first transistor and a second transistor, the circuit comprising:

a first resistor connected between a gate and a, drain of the first transistor, the first resistor dropping a first voltage applied to the gate of the first transistor to a second voltage applied to the drain of the first transistor,

a second resistor connected between a gate and a drain oldie second transistor, the second resistor dropping a third voltage applied to the gate of the second transistor to a fourth voltage applied to the drain of the second transistor, and

a third resistor connected between the gate of the first transistor and the gate of the second transistor, the first resistor dropping the first voltage to the third voltage.

2. A circuit as defined by claimed 1, wherein the first resistor establishes a first voltage drop, the second resistor establishes a second voltage drop, and the first voltage drop is equal to the second voltage drop.

3. An integrated circuit including a test circuit for resting a plurality of transistors including a first transistor and a second transistor, the test circuit comprising:

a first resistor connected between a gate and a drain of the first transistor, the first resistor dropping the first voltage applied to the gate oldie first transistor to a second voltage applied to the drain of the first transistor;

a second resistor connected between a gate and a drain of the second transistor, the second resistor dropping the third voltage applied to the gate of the second transistor to a fourth voltage applied to the drain of the second transistor; and

a third resistor connected between the gate of the first transistor and the gate of the second transistor, the first resistor dropping the first voltage to the third voltage.

4. A circuit as defined by claimed 3, wherein the first resistor establishes a first voltage drop, the second resistor establishes a second voltage drop, and the first voltage drop is equal to the second voltage drop.