Output overvoltage protection circuit for power amplifier

• US 7,145,397 B2
• Filed: 07/13/2004
• Issued: 12/05/2006
• Est. Priority Date: 08/08/2003
• Status: Active Grant

• Current Assignee: Murata Manufacturing Co Limited
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Yamamoto, Kazuya, Suzuki, Satoshi, Shimura, Teruyuki, Asada, Tomoyuki
• Primary Examiner(s): Mottola, Steven J.
• Application Number:
  US10/889,059
• Publication Number:
  US 20050030106A1
• Time in Patent Office: 875 Days
• Field of Search: 330/207.P, 330/298, 455/117
• US Class Current: 330/298
• CPC Class Codes: H03F 1/52 Circuit arrangements for protecting such amplifiers monitoring arrangements G01R31/28; increasing reliability in communication systems, e.g. using redundancy H04B1/74

Abstract

Disclosed is an output overvoltage protection circuit for a power amplifier having a plurality of stages, which comprises a monitor circuit for monitoring an output overvoltage of an output transistor in the final stage of the power amplifier and allowing a current to flow therethrough in response to the monitored output overvoltage, and a current mirror circuit for supplying a current proportional to the current from the monitor circuit in such a manner that the base bias of the first-stage transistor of the power amplifier is reduced in response to the current supplied from the current mirror circuit, to reduce the output of the final-stage output transistor.

Claims

1. An output overvoltage protection circuit for a power amplifier having a plurality of stages, comprising:

a monitor circuit configured to monitor an output overvoltage of a transistor in one stage of the plurality of stages of said power amplifier, wherein said one stage is not the final stage, and to conduct a current in response to the monitored output overvoltage; and

a current mirror circuit configured to supply a current proportional to the current from said monitor circuit in such a manner that the bias of a first-stage transistor of said power amplifier is reduced in response to the current supplied from said current mirror circuit.

2. The output overvoltage protection circuit according to claim 1, wherein said monitor circuit monitors the output voltage of a second-stage transistor of said power amplifier.

3. The output overvoltage protection circuit according to claim 1, wherein said monitor circuit monitors the output voltage of the first-stage transistor of said power amplifier.

4. The output overvoltage protection circuit according to claim 1, which includes a smoothing circuit configured to smooth said current from the monitor circuit.

5. The output overvoltage protection circuit according to claim 4, wherein a resistor is connected in parallel with a capacitor which forms said smoothing circuit.

7. The output overvoltage protection circuit according to claim 1, wherein said monitor circuit feeds a feedback output to a feedback section through a resistor.

9. The output overvoltage protection circuit according to claim 1, wherein an emitter resistor is connected to one of plural transistors included in the current mirror circuit.

10. The output overvoltage protection circuit according to claim 1, wherein the monitor circuit comprises a diode.

6. An output overvoltage protection circuit for a power amplifier having a plurality of stages, comprising:

a monitor circuit configured to monitor an output overvoltage of a transistor in one of the plurality of stages of said power amplifier and conduct a current in response to the monitored output overvoltage; and

a current mirror circuit configured to supply a current proportional to the current from said monitor circuit in such a manner that the bias of a first-stage transistor of said power amplifier is reduced in response to the current supplied from said current mirror circuit,

wherein RC notch filter is formed in a base part of two transistors included in the current mirror circuit.

8. An output overvoltage protection circuit for a power amplifier having a plurality of stages, comprising:

a monitor circuit configured to monitor an output overvoltage of a transistor in one of the plurality of stages of said power amplifier and conduct a current in response to the monitored output overvoltage; and

a current mirror circuit configured to supply a current proportional to the current from said monitor circuit in such a manner that the bias of a first-stage transistor of said power amplifier is reduced in response to the current supplied from said current mirror circuit,

wherein said monitor circuit further comprises a circuit configured to shunt an input current provided thereto to reduce current flowing through the current mirror circuit.