Semiconductor integrated circuit device

• US 7,145,792 B2
• Filed: 08/26/2005
• Issued: 12/05/2006
• Est. Priority Date: 07/29/2003
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Hokari, Tomofumi, Hasegawa, Masatoshi, Tanaka, Yousuke
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US11/211,543
• Publication Number:
  US 20050281110A1
• Time in Patent Office: 466 Days
• Field of Search: 365/149, 365/203, 365/210
• US Class Current: 365/149
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 11/4099 Dummy cell treatment; Reference voltage generators
• CPC Class Codes: G11C 2207/2227 Standby or low power modes
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: H10B 12/315 with the capacitor higher than a bit line
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures

Abstract

The present invention provides a dynamic RAM which can be operated at a low voltage and realizes the enhancement of a read margin and an area-saving layout. In a memory array including a plurality of memory cells having capacitors which are formed corresponding to a plurality of word lines and a plurality of bit lines, stored information of the memory cell which is read to one bit line out of the pair of bit lines is sensed by a sense amplifier in response to a reference voltage which is formed by a dummy cell connected to another bit line, a precharge voltage of high level or low level corresponding to an operational voltage by a precharge circuit is supplied to the bit lines, and the dummy cells having the same structure as the memory cells are formed at crossing points of word lines for dummy cells and bit lines arranged outside the memory array, MOSFETs which precharge an intermediate voltage between the high level voltage and the low level voltage to the capacitors are provided, and gates of the MOSFETs are connected with charge word lines for dummy cells which are extended in parallel with the word lines for dummy cells.

Claims

1. A semiconductor integrated circuit device having a memory circuit comprising:

a memory array including;

a plurality of word lines,

a first dummy word line,

a second dummy word line,

a plurality of bit lines across the plurality of word lines, the first dummy word line, and the second dummy word line,

a plurality of memory cells each having a first capacitor and a first MOSFET, a source and a drain of the first MOSFET being coupled between one of the plurality of bit lines and a storage node of the first capacitor, and a gate of the first MOSFET being coupled to one of the plurality of word lines, and

a plurality of dummy memory cells each having a second capacitor, a second MOSFET, and a third MOSFET, a source and a drain of the second MOSFET being coupled between one of the plurality of bit lines and a storage node of the second capacitor, a gate of the second MOSFET being coupled to the first dummy word line, a source and a drain of the third MOSFET being coupled between the storage node of the second capacitor and a reference voltage, and a gate of the third MOSFET being coupled to the second dummy word line;

a plurality of sense amplifiers each provided corresponding to one of the plurality of bit lines, sensing a difference between a signal read out from a selected memory cell and a signal read out from one of the plurality of dummy memory cells, and amplifying the signal read out from the selected memory cells to a first voltage or a second voltage; and

a precharge circuit supplying the first voltage to the plurality of bit lines,

wherein the reference voltage is between the first voltage and the second voltage.

2. A semiconductor integrated circuit device according to claim 1,

wherein the first dummy word line and the second dummy word line are formed at the same line pitch as the plurality of word lines.

3. A semiconductor integrated circuit device according to claim 2, further comprising:

a diffusion layer provided outside of the first and second dummy word line and supplied the reference voltage,

wherein one of the source or the drain of the third MOSFET is extended to the diffusion layer.

4. A semiconductor integrated circuit device according to claim 3,

wherein the diffusion layer is also a guard ring of the memory array.

5. A semiconductor integrated circuit device according to claim 1, further comprising:

a first selective circuit coupled to the first dummy word line; and

a second selective circuit coupled to the second dummy word line,

wherein the first and second selective circuits have a same circuit constitution as a word driver which is coupled to one of the plurality of word lines.

6. A semiconductor integrated circuit device according to claim 5,

wherein the second dummy word line is set to a selective level to make the third MOSFET assume an ON state during a predetermined term within a precharge term of a precharge circuit supplying to the plurality of bit lines, and is set to a non-selective level in another term.

7. A semiconductor integrated circuit according to claim 6,

wherein a channel length of MOSFETs included in the first and second selective circuits is larger than a channel length of MOSFETs included in the word driver.

8. A semiconductor integrated circuit according to claim 4,

wherein a portion of the diffusion layer is formed into silicide.

9. A semiconductor integrated circuit according to claim 1,

wherein the first capacitor is a stacked capacitor.