Nonvolatile memory system, semiconductor memory, and writing method

• US 7,145,805 B2
• Filed: 01/31/2006
• Issued: 12/05/2006
• Est. Priority Date: 07/09/1996
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi ULSI Engineering Corp, Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Ishii, Tatsuya, Tsuchiya, Osamu, Miwa, Hitoshi, Kubono, Shooji
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Nguyen, Hien N
• Application Number:
  US11/342,885
• Publication Number:
  US 20060120164A1
• Time in Patent Office: 308 Days
• Field of Search: 365/185.24, 365/185.02, 365/185.29, 365/230.08
• US Class Current: 365/185.24
• CPC Class Codes: G11C 16/0491 Virtual ground arrays
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2216/18 Flash erasure of all the cells in an array, sector or block simultaneously

Abstract

A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation, performing the additional writing operations quicker than the usual writing operation, and lightening the burden imposed on software for use in additional writing. The data stored in a designated sector is read out before being saved in a register, and the selected sector is subjected to single-sector erasing when a predetermined command is given. Then write expected value data is formed from the saved data and data to be additionally written, completing the writing operation.

Claims

1. A nonvolatile memory comprising:

a plurality of nonvolatile memory cells, each of which has an arbitrary one of a program state and an erase state, being divided into a plurality of blocks;

a plurality of input/output terminals;

a command decode circuit which is capable of decoding an arbitrary one of plural commands received via said plurality of input/output terminals;

a plurality of word lines; and

a control circuit,

wherein a capacity of each of said plurality of blocks is more than 512 bytes,

wherein said control circuit is capable of performing a consecutive write operation within the same block without an intervening erase to said nonvolatile memory cells,

wherein said intervening erase is that said control circuit controls selection of an arbitrary one of said blocks and a moving state of said nonvolatile memory cells belonging in the selected one block to said erase state in response to an erase command,

wherein said consecutive write operation is that said control circuit controls selection of a first word line and a moving state of first ones of said nonvolatile memory cells coupled to said first word line to said program state in accordance with data in response to a write command accompanied with first address information, and then, said control circuit controls selection of said first word line and a moving state of second ones of said nonvolatile memory cells coupled to said first word line to said program state in accordance with data in response to said write command accompanied with second address information, and

wherein said write command is capable of being accompanied with 512-byte data.

2. A nonvolatile memory according to claim 1, further comprising a buffer circuit,

wherein said buffer circuit is coupled to said plurality of input/output terminals, and is capable of storing data temporarily.

3. A nonvolatile memory according to claim 1,

wherein each of said blocks includes a data storing area and a management data storing area.

4. A nonvolatile memory according to claim 3, further comprising an address decoder, wherein said address decoder decodes said first address information and said second address information for selecting said first word line.

5. A nonvolatile memory according to claim 4,

wherein said control circuit controls performance of a verify operation for detecting whether each of said nonvolatile memory cells coupled to said first word line has been moved into said program state or not.