Asynchronous data pipe for automatically managing asynchronous data transfers between an application and a bus structure

• US 7,145,921 B2
• Filed: 01/16/2003
• Issued: 12/05/2006
• Est. Priority Date: 03/07/1996
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.), Sony Electronics Inc. (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.), Sony Electronics Inc. (Sony Group Corp.)
• Inventors: Smyers, Scott D.
• Primary Examiner(s): Patel, Ajit
• Application Number:
  US10/346,657
• Publication Number:
  US 20030123475A1
• Time in Patent Office: 1,419 Days
• Field of Search: 370/466, 370/471, 370/474, 370/432, 370/903, 370/535, 370/537, 370/465, 370/252, 370/254, 370/384, 370/344, 370/398, 370/428, 370/411, 370/536, 710/126, 710/124, 710/100, 710/112, 709/228, 395/280, 395/285, 395/287, 395/290, 395/244, 395/410, 395/421.1, 395/824, 395/306, 395/307
• US Class Current: 370/536
• CPC Class Codes: G06F 13/128 for dedicated transfers to a network for protocol converters G06F13/387
• CPC Class Codes: H04L 12/40071 Packet processing; Packet format adaptation of digital video signals for transport over a specific network H04N21/2381, H04N21/4363, H04N21/4381; packet switches H04L49/00; intermediate storage or scheduling H04L49/90
• CPC Class Codes: H04L 12/6418 Hybrid transport

Abstract

An asynchronous data pipe (ADP) automatically generates transactions necessary to complete asynchronous data transfer operations for an application over a bus structure. The ADP includes a register file which is programmed and initiated by the application. The register file includes the bus speed, transaction label, transaction code, destination node identifier, destination offset address, length of each data packet, packet counter, packet counter bump field, control field and a status field. During a data transfer operation, the ADP generates the transactions necessary to complete the operation over the appropriate range of addresses, using the information in the register file as a template. The ADP increments the value in the destination offset address field for each transaction according to the length of each data packet, unless the incrementing feature has been disabled and the transactions are to take place at a fixed address. The packet counter represents the number of transactions remaining to be generated. The packet counter value is decremented after each packet of data is transferred. The application can increment the packet counter value by writing to the packet counter bump field. A multiplexer is included within a system having multiple ADPs for multiplexing the information from the ADPs onto the bus structure. A demultiplexer is included within a system having multiple ADPs for routing information from the bus structure to the appropriate ADP.

Claims

1. An asynchronous data pipe configured for coupling between an application and a bus structure for automatically controlling asynchronous data transfer operations to and from the application over the bus structure comprising:

a. means for receiving parameters regarding a data transfer operation;

b. means for automatically generating transactions necessary to complete the data transfer operation between the application and a node coupled to the bus structure, without direct processor control; and

c. a register file in which the application stores the parameters regarding the data transfer operation, using the register file as a template for generating the transactions necessary to complete the data transfer operation and further wherein the parameters within the register file include a destination address in an address space of the bus structure, a length of data to be transferred, a length of each data packet to be transferred and a direction of the transfer.

2. The asynchronous data pipe as claimed in claim 1 wherein the transactions necessary to complete the data transfer operation are generated to an increasing range of addresses, by incrementing the destination address by the length of each data packet when each transaction is generated.

3. The asynchronous data pipe as claimed in claim 1 wherein the transactions necessary to complete the data transfer operation are generated to a fixed address.

4. The asynchronous data pipe as claimed in claim 1 wherein the register file further includes a packet counter value representing a number of packets remaining to be transferred.

5. The asynchronous data pipe as claimed in claim 4 wherein the application automatically increments the packet counter value by writing to a predetermined field in the register file.

6. A method of managing a write data transfer operation between an application and a node coupled to a bus structure, independent of direct processor control and intervention by the application, comprising:

a. receiving parameters regarding a write data transfer operation from the application, wherein the parameters received from the application are stored in a register file and further wherein the parameters include the destination address, a length of data to be transferred, a length of each data packet to be transferred and a packet counter value representing a number of packets to be transferred;

b. obtaining a packet of data from the application;

c. adding a header to the packet of data, specifying a destination address of the packet of data; and

d. transferring the packet of data, including the header, onto the bus structure, using the register file as a template for generating the transaction necessary to write a packet of data onto the bus structure.

7. The method as claimed in claim 6 further comprising:

e. increasing the destination address by the length of a data packet;

f. decrementing the packet counter value; and

g. repeating steps b–

f for each packet of data to be transferred until the packet counter value is equal to zero.

8. The method as claimed in claim 7 further comprising a data memory buffer loaded by the application, wherein the packet of data is obtained from the data memory buffer.

9. A method of managing a read data transfer operation between an application and a node coupled to a bus structure comprising:

a. receiving parameters regarding a read data transfer operation from the application;

b. generating a transaction necessary, independent of direct processor control and intervention by the application, in order to request that a packet of data from the node be placed on the bus structure;

c. transfering the transaction onto the bus structure;

d. obtaining the packet of data from the bus structure;

e. stripping header information from the packet of data; and

f. providing the packet of data without the header information to the application.

10. The method as claimed in claim 9 wherein the parameters received from the application are stored in a register file.

11. The method as claimed in claim 10 wherein the parameters include a destination address, representing an address at the node where the data is to be sent from, a length of data to be transferred, a length of each data packet to be transferred and a packet counter value representing a number of packets to be transferred.

12. The method as claimed in claim 11 wherein the register file is used as a template for generating the transaction necessary to read a packet of data from the node.

13. The method as claimed in claim 12 further comprising:

f. increasing the destination address by the length of a data packet;

g. decrementing the packet counter value; and

h. repeating steps b–

g for each packet of data to be transferred until the packet counter value is equal to zero.

14. The method as claimed in claim 13 wherein the packet of data is provided to the application through a data memory buffer.

15. An apparatus for managing asynchronous data transfer operations between one or more applications and a bus structure comprising:

a. a plurality of asynchronous data pipes configured for coupling between the one or more applications and the bus structure, each including;

i. means for receiving parameters configured for coupling to the application for receiving parameters regarding a data transfer operation; and

ii. means for automatically generating transactions necessary to complete the data transfer operation without direct processor control;

b. a physical bus interface configured for coupling to the bus structure for placing data on the bus structure and obtaining data from the bus structure;

c. a multiplexing circuit coupled between each asynchronous data pipe and the physical bus interface for transmitting data packets from the asynchronous data pipes to the bus structure; and

d. a demultiplexing circuit coupled between each asynchronous data pipe and the physical bus interface for routing data packets obtained from the bus structure to an appropriate one of the asynchronous data pipes.

16. The apparatus as claimed in claim 15 wherein each asynchronous data pipe further comprises a register file in which data and parameters regarding the data transfer operation are stored.

17. The apparatus as claimed in claim 16 wherein the data and parameters are stored in the register file by one of the applications.

18. The apparatus as claimed in claim 16 wherein the register file includes a destination address in an address space of the bus structure, a length of data to be transferred, a length of each data packet and a direction of the data transfer.

19. The apparatus as claimed in claim 18 wherein the register file further includes a transaction label value for the asynchronous data pipe and further wherein each of the asynchronous data pipes have a unique transaction label value.

20. The apparatus as claimed in claim 18 wherein the register file further includes a range of transaction label values for the asynchronous data pipe and further wherein each of the asynchronous data pipes have a unique range of transaction label values.

21. The apparatus as claimed in claim 19 wherein the register file is used as a template for generating the transactions necessary to complete the data transfer operation.

22. The apparatus as claimed in claim 21 wherein the demultiplexing circuit determines the appropriate asynchronous data pipe to which a data packet should be routed by the transaction label value within the data packet.

23. The apparatus as claimed in claim 22 wherein the demultiplexing circuit determines the appropriate asynchronous data pipe to which a write response packet should be routed by the transaction label value within the data packet.

24. The apparatus as claimed in claim 22 wherein the transactions necessary to complete the data transfer operation are generated to an increasing range of addresses, by increasing the destination address by the length of each data packet when each transaction is generated.

25. The apparatus as claimed in claim 22 wherein the transactions necessary to complete the data transfer operation are generated to a fixed address.

26. The apparatus as claimed in claim 22 wherein the bus structure is an IEEE 1394 standard bus structure.

27. An asynchronous data pipe configured for coupling between an application and an IEEE 1394 standard bus structure for managing asynchronous data transfer operations to and from the application over the bus structure comprising:

a. a register file;

b. a programming circuit coupled to the register file and configured for coupling to the application for receiving parameters regarding a data transfer operation from the application and storing the parameters in the register file; and

c. an automatic transaction generating circuit coupled to the register file for automatically generating transactions necessary to complete the data transfer operation using information in the register file as a template.

28. The asynchronous data pipe as claimed in claim 27 wherein the register file includes a destination address, a length of data to be transferred, a length of each data packet to be transferred and a direction of the transfer.

29. The asynchronous data pipe as claimed in claim 28 wherein the transactions necessary to complete the data transfer operation are generated to an increasing range of addresses.

30. The asynchronous data pipe as claimed in claim 28 wherein the transactions necessary to complete the data transfer operation are generated to a fixed address.

31. The asynchronous data pipe as claimed in claim 28 wherein the register file further includes a packet counter value representing a number of packets remaining to be transferred, wherein the packet counter value is decremented after each packet of data is transferred.

32. The asynchronous data pipe as claimed in claim 31 wherein the application automatically increments the packet counter value by writing to a predetermined field in the register file.

33. An apparatus for managing asynchronous transfers between a processor and a bus structure, comprising:

a. a plurality of means for coupling between a processor and a bus structure, each including means for receiving from the processor a request for an asynchronous transfer and for generating in response thereto a series of transactions on the bus structure;

b. means for transmitting data packets of the transactions from any of the coupling means to the bus structure; and

c. means for routing data packets of the transactions from the bus structure to a corresponding one of the coupling means, the correspondence being based on a label value of the transaction.

34. The apparatus as claimed in claim 33 wherein the bus structure is an IEEE 1394 standard bus structure.

35. An apparatus for managing asynchronous transfers between a processor and a bus structure, comprising:

a. a plurality of circuits each coupled between a processor and a bus structure, each being configured to receive from the processor a request for an asynchronous transfer and to generate in response thereto a series of transactions on the bus structure;

b. a multiplexor configured to transmit data packets of the transactions from any of the circuits to the bus structure; and

c. a demultiplexor configured to route data packets of the transactions from the bus structure to a corresponding one of the circuits, the correspondence being based on a label value of the transaction.

36. The apparatus as claimed in claim 35 wherein the bus structure is an IEEE 1394 standard bus structure.