Method and device for protecting integrated circuits against piracy

• US 7,146,509 B2
• Filed: 11/01/2001
• Issued: 12/05/2006
• Est. Priority Date: 12/28/2000
• Status: Active Grant

• Current Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Inventors: Marinet, Fabrice, Wuidart, Sylvie
• Primary Examiner(s): Moazzami, Nasser
• Assistant Examiner(s): Cervetti, David Garcia
• Application Number:
  US10/004,527
• Publication Number:
  US 20020124183A1
• Time in Patent Office: 1,860 Days
• Field of Search: 713/194
• US Class Current: 713/194
• CPC Class Codes: G06F 21/755 with measures against power attack
• CPC Class Codes: G06F 2221/2143 Clearing memory, e.g. to prevent the data from being stolen

Abstract

Before a predetermined processing sequence, the integrated circuit detects the state of at least one timer. The circuit controls the activation of the timer if it is not activated, and disables itself if the timer is activated.

Claims

1. A method of protecting an integrated circuit against piracy, the integrated circuit comprising a central processing unit (CPU) and at least one associated timer, the method comprising:

at the CPU, performing an initialization processing sequence;

at the CPU, detecting the state of the at least one timer after performing the initialization processing sequence and before performing a predetermined processing sequence;

if the at least one timer is not activated, activating the at least one timer and performing the predetermined processing sequence; and

if the at least one timer is activated, disabling the integrated circuit.

2. The method according to claim 1, further comprising the CPU deactivating the at least one timer after performance of the predetermined processing sequence.

3. The method according to claim 1, further comprising:

the CPU modifying the value of a counter within a protected area in a non-volatile memory if it is detected that the at least one timer is activated;

the CPU comparing the counted value with a predefined threshold; and

the CPU performing a process for protecting confidential data stored within memories in the integrated circuit if the counted value reaches the predefined threshold.

4. The method according to claim 3, wherein the protection process comprises erasing the confidential data from the memories in the integrated circuit.

5. The method according to claim 3, wherein the protection process comprises erasing a secret code stored within a memory in the integrated circuit.

6. The method according to claim 3, wherein the protection process comprises erasing all memories in the integrated circuit.

7. The method according to claim 1, wherein the at least one timer comprises a plurality of timers each being associated with a respective authentication calculation of a sequence of a predefined number of calculations;

and further comprising;

the CPU detecting the state of a respective timer before performing an associated calculation,

the CPU activating the respective timer if it is not activated; and

the CPU disabling the integrated circuit if the respective timer is activated.

8. An integrated circuit (IC) comprising:

a central processing unit (CPU); and

at least one timer circuit for protecting the IC against piracy and comprising

a timer which is activated when the IC is powered-on and for a predetermined duration when the IC is powered-off,

a timer activating circuit for activating the timer,

a timer deactivating circuit for deactivating the timer, and

a detection circuit for detecting the state of the timer;

the CPU detecting the state of the timer after performing an initialization processing sequence and before performing a predetermined processing sequence, and, if the timer is not activated, activating the timer and performing the predetermined processing sequence; and

the CPU disabling the IC at predefined times if the timer is in the activated state.

9. The integrated circuit according to claim 8, wherein the CPU deactivates the timer after normal execution of the predetermined processing sequence.

10. The integrated circuit according to claim 8, wherein each timer circuit further comprises:

a power supply detection circuit for detecting a power supply; and

a timer control device for allowing the timer to be activated or deactivated when the power supply is detected during a predetermined time period.

11. The integrated circuit according to claim 8, wherein the at least one timer circuit comprises a plurality of timer circuits each being associated with an authentication calculation performed by the CPU;

and wherein the CPU determines, before each calculation, the state of the associated timer, and activates the associated timer if it is not activated, and disables the IC if the associate timer is activated.

12. The integrated circuit according to claim 8, wherein the at least one timer circuit comprises:

a capacitor;

a discharge circuit associated with the capacitor and designed to discharge over the predetermined duration when the IC is powered-off;

a circuit for detecting capacitor charging;

a capacitor charging control circuit; and

a capacitor discharging control circuit.

13. The integrated circuit according to claim 12, wherein the capacitor discharging control circuit discharges the capacitor faster than when the IC is powered-off.

14. The integrated circuit according to claim 12, wherein the at least one timer circuit further comprises a MOS transistor associated with the capacitor so that it is only discharged by a leakage current when the IC is powered-off.

15. The integrated circuit according to claim 8, further comprising a test circuit for reducing the predetermined duration of the timer during a testing procedure.