Data structures for representing the logical and physical information of an integrated circuit

• US 7,146,595 B2
• Filed: 03/12/2004
• Issued: 12/05/2006
• Est. Priority Date: 03/03/2004
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Knol, David A., Raje, Salil Ravindra
• Primary Examiner(s): Siek, Vuthe
• Assistant Examiner(s): Levin, Naum B.
• Application Number:
  US10/800,042
• Publication Number:
  US 20050204315A1
• Time in Patent Office: 998 Days
• Field of Search: 716 8- 11
• US Class Current: 716/119
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

A floor planner tool for integrated circuit design which provides tools and displays for a designer to create a floor plan to define desired placement of circuits defined in a logical netlist by creating a physical hierarchy comprised of nested pblocks. Each pblock is a data structure which contains data which defines which circuits from the logical netlist are assigned to it. Each pblock stands alone and can be input to a place and route tool without the rest of the physical hierarchy. Each pblock data structure contains pointers to the circuits on the netlist assigned to that plbock, identifies other pblocks nested within it and contains at least a list of boundary pins for that pblock. Net data structures in the physical hierarchy define which nets are connected to which pins. PCellview data structures define the internal structure of each pblock.

Claims

1. A computer readable medium having stored thereon a data structure defining a physical block (pblock) in a hierarchy of pblocks (both parent and child) which defines the same integrated circuit structure by reference to data in a netlist which defines a logical hierarchy, the data defining said pblock comprising:

A) a set of pointers to data defining boundary pins of said pblock, said boundary pins for connecting to nets external to the pblock and for connecting to nets internal to the pblock;

B) a field containing a pointer to a first parent physical block cellview (pcellview) which contains said pblock;

C) a field containing a pointer to a second pcellview data structure owned by said pblock, said second pcellview containing pointers to data which define lists of pins internal to the pblock, nets that connect to the internal pins and boundary pins of the pblock, child pblocks and child instances which have been assigned to said pblock and which define the functionality of said pblock; and

D) a field containing coordinates on a floorplan representing a surface of an integrated circuit on which circuits assigned to said pblocks are to be formed, said coordinates to define a geometric shape representing said pblock and the size thereof, said geometric shape being displayed on a computer display of a computer executing a floor planning process.

2. The computer readable medium of claim 1 wherein the data structure further includes data pointers to data which define internal pins of instances contained within said pblock.

3. The computer readable medium of claim 1 wherein said data structure includes a pcellview data structure comprising:

E) a list containing data which defines a list of pblocks which are included or nested within said pblock defined by data elements A through D;

F) a list containing data or pointers to data on said netlist which define instances which have been assigned to said pblock;

G) a list containing data or pointers to data which define boundary pins of said pblock which connect to internal nets of said pcellview;

H) wherein the list containing pointers to data which define internal physical nets which connect from boundary pins of said pblock to internal pins completes the original connectivity between instances defined in said netlist; and

I) a field which contains a pointer to a data object representing a parent pblock that envelopes the pcellview data object defined by data elements E through I.

4. A computer readable medium having stored thereon a data structure defining a physical block cellview (pcellview) owned by a particular pblock in a hiearchy of pblocks which defines the internals of said pblock which owns said pcellview, the data defining said pcellview comprising:

A) a list containing data which defines a list of pblocks which are included or nested within said pblock defined by data elements A through D;

B) a list containing data or pointers to data on a netlist which define instances which have been assigned to said pblock;

C) a list containing pointers to data which define boundary pins of said pblock which connect to internal nets of said pcellview and to external nets of said pblock;

D) a list containing pointers to data which define internal physical nets which connect from boundary pins of said pblock to internal pins of said pblock so as to complete the original connectivity between instances defined in said netlist; and

E) a field which contains a pointer to a data object representing a parent pblock that envelopes the pcellview data object defined by data elements A through E.

5. A processor-based method for representing a netlist that defines a logical hierarchy, comprising:

creating in a memory respective representations of a plurality of physical blocks (pblocks), wherein each pblock specifies,

a set of boundary pins of the pblock, the boundary pins for connecting to nets external to the pblock and for connecting to nets internal to the pblock;

a reference to a first parent physical block cellview (pcellview) that contains said pblock;

a reference to a second pcellview owned by the pblock, the second pcellview specifying lists of pins internal to the pblock, nets that connect to the internal pins and boundary pins of the pblock, child pblocks and child instances assigned to said pblock and that define the functionality of the pblock; and

a set of coordinates representing a surface of an integrated circuit on which each circuit assigned to the pblock is to be formed.

6. The method of claim 5, further comprising:

displaying instances of the netlist in a first pane on a display and the pblocks in a second pane on the display; and

highlighting display of instances of the netlist that are assigned to pblocks.